DS160PT801: DS160PT801X16 EVM test

Hi David, Evan,

Could you please help take a look at it?

And after you replying and Sam can go through message with you. 
Thank you!

Hi Zoe,

We are looking into the issue and will get back to you as soon as possible. I believe David is currently in Taipei for a customer visit, so while he may not have much bandwidth this week I will let him know.

Best,

Evan Su

Hi Zoe,

The current IOMT report seems to be cut off (formatting problem from the PDF generation?), but from what I can see the test is in the grey zone, borderline with the passing criteria. It says that this is not a failure but more tests should be run, likely to determine how stable the link is. From the GUI screenshots, it looks like the eye measurements seen by the retimer output are OK, but some lanes have more difficulties than others.

Can the customer run a few more IOMT tests and correct the report formatting so we can see more details? If there is an option to test each of the 4 PCIe lanes individually, that would be good too.

Best,

Evan Su

Hi Evan,

Will ask Sam to reply here.

Thanks!

Hi All:

  Good day. I just confirm IOMT fails can't mean PCIE Gen4 signal fails. 

So, let's go back the TI GUI tool. How to get the good eye diagram from your GUI tool with the re-timer demo board? Thank you.

Hi Sam,

There is not much device adjustment that can be done from the GUI. CTLE and receiver DFE are automatically tuned and usually it is not beneficial to override them. TX presets are also automatically negotiated as part of the PCIe link, it is possible to override them but I would need to check with my team first because I have not done that before.

From the screenshot, it looks like channel A4 and channel A7 (both downstream) have the smallest eye measurements, so I would assume that they are the ones affecting the IOMT tests the most. A7 has the smallest eye width at 0.59 UI when seen at the retimer output and I see that it has a TX preset of 6:7:0 = P9, which is one of the strongest. My guess is that A7 has more loss between the retimer and the CPU, and the retimer and link are trying hard to open the eye already. If this is true, then it is difficult to push them further and we would typically review the board layout to see what can be improved.

Can you run IOMT as I suggested in a way that can check the performance of each lane? It is still helpful to see if all lanes are marginal or just 1-2 of them.

Best,

Evan Su

Hi Evan:

  Sorry, Intel IOMT tool can't test each lane. IOMT tool only can test total PCIE BUS. BTW. IOMT tools is not a standard criteria for PCIE Gen4. We need to check  how to pass the eye monitor page in the TI SigCON Architect 3.1. Thank you.

Best Regards,

Sam Lee