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ISO7240C Output while start up power rising period

Other Parts Discussed in Thread: ISO7240C, ISO7240CF

Hello,

I would like to make sure output is "Z" or not while Vcc2 power rising/falling period.

(1) While in Vcc2 (Output Vcc) power rising period (0V to 5V), output keeps "Z". (EN=Low, Input=Irrelevant)  Is this correct?

(2) While in Vcc2 (Output Vcc) power falling period (5V to 0V), output keeps "Z". (EN=Low, Input=Irrelevant)  Is this correct?

(3) If above are correct, I understand "output = Z" is independent of Vcc1 (Input Vcc).  Is this correct?

 

I concern while in Vcc2 power rising/falling preiod, the output goes to unexpected state like "L" or "H".  That means disable does not work during power rising/falling period.

 2705.ISO7240C.pdf

Regards,

Hide

  • ISO7240C is a default output 'HIGH' device. This means that when the input power, VCC1, is 'OFF' or input signal is lost / open, the output will default to a high state.

    After VCC2 is powered up, the outputs will initially take on a high state. If VCC1 (input supply) is powered up, then it'll take several microseconds for the output to align with input signal or enable status (see specifications for tfs and twake in the datasheet).

     

  • Hello Saleem,

    Thanks for the explanation.

     

    Let me confirm that the explanation is for ISO7240C or ISO7240CF?  (I'd like to know about ISO7240C, not ISO7240CF.)

    I concern incorrect output in an instant even if EN=Low while in Vcc2 powering up from 0V to 5V.

     

    I confirmed output keeps "Z" when EN=Low while in Vcc2 powering up from 0V to 5V on the waveform.  It seems output "Z" state not be independent of Vcc1(Low/High).

    Now, I understand output keeps "Z" when EN=Low while in Vcc2 powering up state and it works correctly, is my understanding correct?

     

    Regards,

    Hide 

     

     

    -----------------------------------------------------------

    Additional Explanation

     

    Let me summarize my question.

    I have two questions on ISO7240C. (not ISO7240CF)

    First, I'd like to confirm output is always "Z"or not whenever enable is low.  On the above function table, I can see output is always "Z" if enable is low regardless of powered up or powered down of Input Vcc(Vcc1).  It seems that enable function is relevant with output Vcc(Vcc2), and not relevant with input Vcc(Vcc1).  Thus I predict output is always "Z" whenever output Vcc(Vcc2) is powered up and enable is low, and it does not relevant with input Vcc(Vcc1).  Is this correct?  (Please refer to the below table (A))

    Second, I'd like to confirm output keeps "Z" or not while Vcc(Vcc2) voltage rising from 0V to 5V.  On my test, I confirmed output keeps "Z" while in the voltage rising term if enable is low.  Is this right behave on this device?  (Please refer to the below table (B))

     

    Regards,

    Hide

  • Hi Hide,

    We'll simulate this condition so we can provide you this information as accurately as possible. We'll get this information to you by next Friday.

     

  • Hello Hid,

    in the FILES of this forum (See above) you can also download a short article on ISOLTOR OUTPUT CONDITIONS DURING POWER-UP.

    regards,

    Thomas

  • Hello Thomas,

     

    Thanks for the information about ISO72xx OUTPUT CONDITIONS DURING POWER-UP.

    I guess this article describes an output condition between Vcc and output and does not describe relevant with Output Enable.

    So, I still hope to get your simulation result on the below condition.

     

    Again, my question are as follows.  (Question on ISO7240C, not ISO7240CF)

    First, I'd like to confirm output is always "Z"or not whenever enable is low.  On the above function table, I can see output is always "Z" if enable is low regardless of powered up or powered down of Input Vcc(Vcc1).  It seems that enable function is relevant with output Vcc(Vcc2), and not relevant with input Vcc(Vcc1).  Thus I predict output is always "Z" whenever output Vcc(Vcc2) is powered up and enable is low, and it does not relevant with input Vcc(Vcc1).  Is this correct?  (Please refer to the below table (A))

    Second, I'd like to confirm output keeps "Z" or not while Vcc(Vcc2) voltage rising from 0V to 5V.  On my test, I confirmed output keeps "Z" while in the voltage rising term if enable is low.  Is this right behave on this device?  (Please refer to the below table (B))

    Regards,

    Hide

     

  • Hide,

    The answer to your first question is 'Yes'. So if Enable is low, the output will be 'Z' state if VCC2 is already powered up.

    We'll need to simulate the 2nd condition and the answer will likely depend on the VCC2 ramp rate from 0V to 5V. Can you please provide the ramp rate of VCC2?

  • Hi Saleem,

    Thanks for the information.

     

    The Vcc2 ramp rate is "1ms to 2000ms" .

    Can you please simulate following conditions?

    (1)  "1ms" for power-up

    (2) "2000ms" for power-up

    (3)  "1ms" for power-down

    (4) "2000ms" for power-down

     

    Thanks in advance.

    Hide

  • Hi Hide,

    Our simulation results show that the device stays in 'Z' or 'High Impedance' state during power up and down conditions that you provided.

  • Hi Saleem,

    Thanks for the information.

    I have confirmed there is no difference between your simulation results and my results.

    I really appreciate your kindly support.

    Hide