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TL16C2552: Interrup Signal

Shinichi Inoue
Guru 21701 points
Part Number: TL16C2552

Dear Specialists,

My customer is evaluating TL16C2552IFN and has a question.

I would be grateful if you could advise.

---

In TL16C2552IFNR,
Interrupt signal continues to be output from UART (TL16C2552)

The data sheet states the following:
>>When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt occurs as follows:
What will happen if the register values are set as shown on the right (FCR0 = 1, IER0 = 1, IER2 = 0)?

In the case of the previously used UART (NS16C552), the specified registers were (FCR0 = 1, IER0 = 1).
Therefore, I would like to check the operation when (FCR0 = 1, IER0 = 1).

---

I appreciate your great help in advance.

Best regards,

Shinichi

  • 0
    TI__Guru 73541 points

    Hi Shinichi,

    Shinichi Inoue said:
    >>When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt occurs as follows:
    What will happen if the register values are set as shown on the right (FCR0 = 1, IER0 = 1, IER2 = 0)?

    The datasheet shows that if you have IER2 = 0, the INT will not trigger based on any receiver line statuses such as overrun, parity issues, framing errors, or break interrupts. You would basically mask any data packet errors received from RX (INT should not trigger/assert for these kind of errors). You should still be able to see them when you read IIR.

    -Bobby

  • 0 in reply to BOBBY
    Guru 21701 points

    Hi Bobby,

    Thank you for your reply.

    I understand IER should not be 0.

    I'll share your answer with the customer.

    When they have an additional question, I consult you again.

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi 

  • +1 in reply to Shinichi Inoue
    TI__Guru 73541 points

    Hi Shinichi,

    Shinichi Inoue said:
    I understand IER should not be 0.

    It depends on how the customer is their software setup. Some customers don't use the interrupt and poll the device every once in a while. If you "know" that all communication sent to you is reliable then setting IER2=0 can be okay. My understanding is you should get similar behavior between both devices even if IER2 is set in one and not set in another if the data received from RX isn't corrupted or overrun.

    -Bobby

  • 0 in reply to BOBBY
    Guru 21701 points

    Hi Bobby,

    The customer has an additional question.

    Could you please advise?

    ---

    We checked the log at the time of occurrence of the event where the interrupt signal from UART (TL16C2552) continues.

    ・When the value of IIR is 4 (Received data available) or C (Character time-out indication), the value of Bit 1 (DR) of LSR is 0
    　
    Is it possible to take values like the above?
    Please let us know under what circumstances.

    ---

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi

  • 0 in reply to Shinichi Inoue
    TI__Guru 73541 points
    Shinichi Inoue said:

    We checked the log at the time of occurrence of the event where the interrupt signal from UART (TL16C2552) continues.

    ・When the value of IIR is 4 (Received data available) or C (Character time-out indication), the value of Bit 1 (DR) of LSR is 0

    LSR1 signifies an overrun error occurred; I assume you mean LSR0 (bit 0 of LSR).

    This sounds unusual.. Maybe if you read IIR first then did a read of RHR then read LSR0 you could get something like this. re-reading IIR after this should provide you with 0b1 for IIR though... 

    Is the customer reading IIR AND LSR before going to read the RHR? Or could they be reading one then reading RHR then reading the other? 

    Is the customer able to repeat this issue?

    If they read another byte from the RHR, does IIR reset to 0x01? Is data in RHR after the additional read something they expected to read?

    Curious if they could send a known amount of bytes into RX (like 4 bytes) and verify they read 4 bytes and see if the IIR still states 0x04 or 0x0C. 

    My current thought it the data they are reading is contradicting the other. (One of them seems to be wrong) Unless maybe they are reading them in the wrong order. (like reading IIR then RHR then LSR)

    -Bobby

  • 0 in reply to BOBBY
    Guru 21701 points

    Hi Bobby,

    Thank you for your reply.

    I'll share your suggestion with the customer.

    When I obtain the comment from the customer, I send to you.

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi