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DP83TC813R-Q1: Test data RGMII timing comment

O'Mellin
Expert 6085 points
Part Number: DP83TC813R-Q1

team, customer is testing out the timing they get on the RGMII, it doesnt seem to match our requirement completely, can you please comment ? customer is in cc

I have some other questions about the signal test. Please help confirm them.

Do you think it is acceptable or any risks? any other test methods to optimize?

  1. RGMII RX_D[3:0] rising time and falling time. The test data is the worst values in the test. Each RX signal is NOK

    2. The skew time of RGMII RX_D[3:0] from CLK is also NOK from the test result. the test data is the worst values in the test.

  • 0
    TI__Mastermind 24988 points

    Hi O'Mellin,

    There is some acceptable amount of margin for rise/fall time that should not affect functionality if the setup and hold time requirements are being met.

    However, this is a grey area and we have not validated the margin that rise/fall time requirements can be violated.

    1. 0x456 bits [5] and [0] control the impedance of the RX and TX MAC interface pads, respectively, which impacts the slew rate. 0 is fast mode and 1 is slow mode. Unfortunately, the default is fast mode, and there are no other registers to tune the rise/fall time.

    2. Please confirm the device is strapped into RGMII align mode for this test ( MAC[2:0] = '100' ). Register 0x602[1:0] can also be used to configure RX or TX clock shift/align modes.

    Thank you,

    Evan