TCA9535: Operation of the INT pin

Hi Ryu,

Ryu Yamashita said:

If I set only one input port and all the other ports as outputs, do the INT pins change in conjunction with the input changes?
If this is correct, does it work all the time with no problem as long as I don't go read the register?

Any pin configure to "input" via the configuration register would trigger an interrupt on the /INT pin if the pin state is changed from the original. 

A read of the input port register would then clear this interrupt. 

Writing to the output port register would not trigger the interrupt on /INT. 

Ryu Yamashita said:

Also, if there is a power outage that does not cause a POR, can the register be rewritten and it will work fine?
Is there a possibility of data corruption if POR is not applied?

I think you are referring to a possible brown out case where power dips on VCC and could potentially conduct a power on reset to the I2C state machine. 

To ensure the device does not reset itself due to brown out, the parameters in table 9-1 need to be followed for glitch width and glitch height on VCC. 

These are found in section 9 Power supply Recommendations in the datasheet. 

Ryu Yamashita said:

The operation of the INT pin has a maximum delay of 4μs. Does this depend on the speed of SCL?

Specs like "tir" I believe are dependent on the operating temperature of the device which would effect the characteristics of the components inside the IC, increasing/decrease prop delays based on temperature. 

I don't believe SCL plays a role in the <4us delay, but I could be wrong here. This would be something that would need to be looked at on the bench or in sim data. 

Ryu Yamashita said:

What does "Unstable data" mean in the "Write mode" section on p. 13 of the datasheet?
Does it mean that writing is disabled during ACK?

From figure 7-3...

What this diagram is saying is that upon the 9th clock cycle in an I2C transaction, assuming the device ACK's, there is a delay of time from 70% of VCC on SCL for time tPV where the data on the p-ports is unstable. 

In other words, once an ACK occurs, the user of the device must wait a tpV < 200ns or 300ns before data on the p-ports is stable. For example, the user writes to the IO expander to change an output pin from high logic to low logic. After the 9th clock cycle or ACK bit, 300ns must pass by to be sure that the p-port is outputting the correct stable logic on Pn.

If somehow you were able to read the state of the p-port Pn directly after the ACK bit, there is not guarantee that the state of that output is correct until you have waited 300ns. 

Regards,

Tyler

Hi Ryu,

Ryu Yamashita said:

In 7.3.3 of the datasheet it says "Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that The data on the port is changed to the original setting or data is read from the port that generated the interrupt.
It says that when the data on the port is changed to the original setting, it is reset. Does this mean that if only one port is left as an input and this one goes from 0 to 1 to 0, the INT signal will behave in the same way?

If only one port pin is left as an input, and it goes from 0 to 1 to 0, the interrupt on /INT will assert (logic low) and de-assert (go back to logic high). The interrupt is lost. 

Ryu Yamashita said:

Regarding POR, I understand the standard of VCC to which POR is applied, but if there is a voltage drop or momentary power failure that does not exceed that standard, does that mean that the device can be used without any problem?

Following the device guidelines for glitch width in the power supply recommendations section of the datasheet guarantees that the device will continue to operate normally under a VCC voltage dip condition. 

Ryu Yamashita said:

Does this mean that the LP filter is temperature dependent?
Also, can you tell me the cutting frequency of the LP filter?

I don't think we have that data on hand, and is not characterized by the datasheet. My recommendation is to design for the maximum specifications in the datasheet to cover all corner cases for this parameter tir. 

Ryu Yamashita said:

One more point about INT, please.
Even if there is no I2C communication, does the INT update stop when SCL stops?

/INT pin is only triggered once an input changes from its original state. Until that pin changes back to its original state, or the input port register is read, then the /INT will keep logic low. 

If no I2C communication is present, /INT still will stay low when SCL stops. 

Regards,

Tyler