DP83867IR: RGMIICTL Default setting

Hi Atsushi,

Can you check Register 0x6E and 0x6F, these are strap registers. Please check these on both boards to confirm that they are strapped in the same modes.

Note that these are extended registers and cannot be read directly. The following FAQ post details the procedure for extended register reads:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1271487/faq-extended-register-space-access-for-ethernet-phys?tisearch=e2e-sitesearch&keymatch=extended%2520register#

Regards,

Alvaro

Hi Reyes,

Thank you for your reply.
I will check this register.
Which bits specifically are relevant?

Hi Reyes,
I checked Register 0x006E and 0x006F.

About Register 0x006E,
the setting value for both boards were the same, "0x0000".
This was as expected.

About Register 0x006F,
the setting value for both boards were the same, "0x0100".
This was not as expected.
The expected value is "0x0000".
Bit[8] is Reserved and default is "0".

I checked other register.
About Register 0x0031,
the board where setting value of register 0x0032 is "0x00D3" is "0x1030".
The board where setting value of register 0x0032 is "0x00D0" is "0x0030".
Bit[5] is Reserved, Default is "0" and Read only but Read value is "1".
Bit[12] is Reserved, Default is "1" and Read only but Read value is "0" at the board where setting value of register 0x0032 is "0x00D0".

Could you find anything from this information?

Hi Reyes,

Thank you for your reply.

I'll try to check register after two type Reset.

Do you mean if even any one bit is different the setting value of register address 0x0032, especially bit[1:0], will change from the default?

Is the Reserved bits no impact?

Hi Atsushi,

If both PHYs are strapped the same then we should expect the registers to be the same. The reserved bits can be ignored for now.

Regards,

Alvaro

Hi Reyes-san,

Read the setting value after Pin Reset, but the result was the same as last time.

Are there any other factors you can think of?

Is it possible that factory default values is different at shipping season?

Hi Atsushi,

I'm almost out of ideas on this one, is the customer facing any functional issues with their boards?

Also, the original discrepancy was with Reg 0x32[1:0], which are the RX/TX CLK Delays. Could you ask the customer to probe the RX/TX Data lines vs the RX/TX CLK and see if it matches the register value?

Regards,

Alvaro