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DS90UB925Q-Q1: serializer interface with DS90UB926 lock connectivity issue

Boopathi M
Prodigy 20 points
Part Number: DS90UB925Q-Q1
Other Parts Discussed in Thread: ALP

Dear team,

Greetings!!!

We are designed our own custom serializer and de-serializer board. As well, We have the DS90UB926 EVK board.

With help of EVK I2C communication we can able to generate display pattern on de-serializer via serializer I2C configuration. So, We ensured both boards and cables are working fine.

We are facing issue, while external(Controller RGB, PCK, DE signal interface with serializer) custom display data generation on de-serializer side using serializer board configuration.

Until pattern generating CDR lock is properly locked. If external PCLK supplied from controller to serializer, then CDR lock link is broken. If external PCLK signal stopped or removed, then CDR lock detected.

Kindly let us clarify below queries ASAP,

  1. In ALP application, While generating patterns – we need to configure the display timing parameter. In this same way, how can we configure the display timing parameters while generating custom display information(i.e Controller data to display)? Shall we use Pattern generator register also for custom display information or any another way to do? 
  1.  If display need 33Mhz PCLK on De-serializer side, then serializer PCLK input also should be in 33MHz range. Is this statement correct? If any wrong in my understanding, kindly let us know formula for serializer PCLK input calculation based on De-serializer output. 
  1. If any example scripting available for this issue, Kindly share to us.

Kindly do needful ASAP.

  • 0
    TI__Mastermind 22946 points

    Hi Boopathi,

    Since PATGEN was working from SER to DES to verify the target timing and no system-level display-side issues, this issue is beyond the devices and might be from the source. Note that the PCLK you want in the display should be the same in SER and source.

    Boopathi M said:

    Until pattern generating CDR lock is properly locked. If external PCLK supplied from controller to serializer, then CDR lock link is broken. If external PCLK signal stopped or removed, then CDR lock detected.

    Did you connect external PCLK after resetting both devices? Was there a specific setup/power up sequence you followed? If the 925-926 does not lock with the external video, the external PCLK may have too much jitter or variation. The other thing to check is whether they are applying video inputs before the power rails are stable. Video inputs can only be applied after power is stabilized on the 925.

    If it is still not working, please share the screenshot of the pattern generator tab where the external timing source is selected.

    Best,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 130 points

    Hi Josh,

    Please find the attached image for pattern generator tab.

  • +1 in reply to Vijay Balaji
    TI__Mastermind 22946 points

    Hi Vijay,

    It seems that the timing source is set to internal timing, not external timing that is from HDMI source. Please check the steps below.

    1. On pattern generator tab, make sure the timing source between external from HDMI source or internal.
    2. Click apply button after video control setting.
    3. Check Enable pattern generator.
    4. Check any option you want.
    5. Check PCLK on information tab for SER and DES are matching the sending PCLK.

    If it is not working with external, please note that you need to check the source as PCLK, jitter, etc.

    Best,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 20 points

    Hi,

    1. We can able to generate color pattern only by the internal timing source. If external timing source is select and apply external source PCLK, then CDR lock is disable.
    2. Yes, We always set mode and IDx pins in low state. So, 15-85MHz frequency ranges selected in both serializer and de-serializer side.
    3. Shall we also use PG register for custom display parameter set?
    4. As per above ALP screen shot, One correction - HSYNC and VSYNC signals are in OFF state. We only drive TFT with DE mode.
    5. How to identify the extra jitter or variation in PCLK? How do we resolve this PCLK jitter or variation issues?

    Note: Issue yet not resolved. Wrongly goes into resolved state. Kindly open it.

  • 0 in reply to Boopathi M
    TI__Mastermind 22946 points

    Hi Boopathi,

    Boopathi M said:
    We can able to generate color pattern only by the internal timing source. If external timing source is select and apply external source PCLK, then CDR lock is disable.

    I mean you need to set display PCLK from HDMI source. As I mentioned again, we need to verify the target timing and no system-level display-side issues from deserializer, then working back towards the SER side by first doing SER PG, then finally end to end. Please confirm if you verified the steps below.

    1. Was PATGEN working from DES to display?
    2. Was PATGEN working SER - DES - display?

    To clarify, could you share display timing parameter? Horizontal/Vertical (Total, Active, Sync width, Back Porch, Front Porch), and Frames/Second

    Boopathi M said:
    Shall we also use PG register for custom display parameter set?

    Please refer to the app note: Exploring the Int Test Pattern Generation Feature of FPDLink III IVI Devices (SNLA132)

    Best,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 20 points

    Hi josh,

    1. We verified below both steps with selection of internal timing source.

    1. PATGEN working fine DES to display - Completed.

    2. PATGEN working fine in sequence of SER - DES- DISPLAY - completed.  (Refer attached ALP - internal timing source image)

            2. External timing source selection PATGEN will not work (Refer attached ALP - External timing source image) FYI, We are always push the Enable generator button. In this image alone, not enabled.

            3. Display Timing parameter for information,

    PCLK – 27MHz

    Total Horizontal width – 928

    Total Vertical width – 525

    Horizontal Active area – 800

    Vertical Active area – 480

    Horizontal sync width – 2

    Vertical sync width – 2

    Horizontal back porch – 22

    Vertical back porch – 5

    Horizontal front porch – 102

    Vertical front porch – 30

    HSYNC –OFF

    VSYNC – OFF

        If possible, kindly arrange the scripting for above timing parameter.

    Thanks

  • 0 in reply to Boopathi M
    TI__Mastermind 22946 points

    Hi Boopathi,

    I'm sorry for the delay on this. It looks like you update the status to be resolved, so I missed the notification about your additional question. I will response it by today.

    Best,

    Josh

  • 0 in reply to Josh Baik
    TI__Mastermind 22946 points

    Hi Boopathi,

    Based on the shared timing, there are the checkpoint from my side.

    • As below, there is margin for horizontal and vertical timing. Please make sure the horizontal/vertical blanking is correct and horizontal/vertical total has to be sum of active and blanking.
    • Also, HSW, HBP, THW must each be divisible by 4, can you double check the timings to see if you can make any adjustments to follow that recommendation? 
    • It said PCLK is 27MHz, but not sure if it is correct since the frame rate would be approx. 55.42  (27M / 928 / 525 = 55.42) What is the desired frame rate?

    Best,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 20 points

    Hi Josh,

    We don't have the recommendations of front and back porch value in datasheet. (Datasheet clock recommendation attached here for your reference.

    Frame rate - 50 to 60 okay for us.

    Initially we are worked with 33MHz with 60fps. Then only moved to 55fps @27MHz. We are tried this initially, but no improvement. whatever the PCLK frequency (27 or 33MHz, if any external PCLK source applied to serializer, then CDR link is broken.

    FYI, with this same timing parameter configuration controller with direct display working fine.

    Do you think this timing parameter and frame rate really affect the CDR link? If anything wants to be remodified for this FPD link, kindly suggest the value. We will try with those value.

    If possible, kindly arrange virtual meeting for clearly understand.

    Thanks.

  • 0 in reply to Boopathi M
    TI__Mastermind 22946 points

    Hi Boopathi,

    For CDR issue, there is an option in register 0x03[1] for PCLK Auto on the 925. This will switch over to an internal OSC when no external PCLK is provided. By default this is enabled, but it is not as stable as an external PCLK signal. This can be turned off by writing 0xD0 to 0x03.

    As I mentioned before, your issue is beyond our devices since it is able to generate patterns from serializer. Again, if the 925-926 does not lock with the external video, the external PCLK may have too much jitter or variation. Also, there are timing margins for horizontal and vertical between total and blanking and we don't know HSW, HBP, and THW each divisible by 4 which is our spec for timing, so we can't say any guarantee to works properly. Please see this E2E thread regarding external PCLK jitter: (Link)

    The other thing to check might be whether they are applying video inputs before the power rails are stable. Video inputs can only be applied after power is stabilized on the 925. but, I don't want you to check this hardware point at this time.

    Below is a script that will enabled patgen with the video timing you attached. This script enabled internal video timing and internal PCLK. The 925 is limited on the precision of its internal PCLK generation. The patgen PCLK is currently 28.6 MHz. The other option is to use patgen with internal timing and external PCLK (from the input pins).

    Fullscreen 925patgen.py Download 
    #925 patgen using internal clock and timing

serAddr = 0x18
desAddr = 0x58

#Patgen setup for (800 * 480 @ ~55 fps)

board.WriteI2C(serAddr, 0x66, 0x03) # N divider
board.WriteI2C(serAddr, 0x67, 0x07)

board.WriteI2C(serAddr, 0x66, 0x04)
board.WriteI2C(serAddr, 0x67, 0xA0)

board.WriteI2C(serAddr, 0x66, 0x05)
board.WriteI2C(serAddr, 0x67, 0xD3)

board.WriteI2C(serAddr, 0x66, 0x06)
board.WriteI2C(serAddr, 0x67, 0x20)

board.WriteI2C(serAddr, 0x66, 0x07)
board.WriteI2C(serAddr, 0x67, 0x20)

board.WriteI2C(serAddr, 0x66, 0x08)
board.WriteI2C(serAddr, 0x67, 0x03)

board.WriteI2C(serAddr, 0x66, 0x09)
board.WriteI2C(serAddr, 0x67, 0x1E)

board.WriteI2C(serAddr, 0x66, 0x0A)
board.WriteI2C(serAddr, 0x67, 0x02)

board.WriteI2C(serAddr, 0x66, 0x0B)
board.WriteI2C(serAddr, 0x67, 0x02)

board.WriteI2C(serAddr, 0x66, 0x0C)
board.WriteI2C(serAddr, 0x67, 0x16)

board.WriteI2C(serAddr, 0x66, 0x0D)
board.WriteI2C(serAddr, 0x67, 0x05)

board.WriteI2C(serAddr, 0x66, 0x0E)
board.WriteI2C(serAddr, 0x67, 0x00)

#Enable patgen
board.WriteI2C(serAddr, 0x65, 0x4) #Patgen use its own video timing and internal PCLK
board.WriteI2C(serAddr, 0x64, 0x1) #Enable patgen

#Enable 926 output
board.WriteI2C(desAddr,0x02, 0x80) #Enable LVCMOS outputs

    Best,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 20 points

    Hi Josh,

    Thanks for your support.

    CDR lock issue has been resolved. Now serializer and de-serializer working fine.

     1. We need to configure I2S_CLK pin as PWM option for backlight dimming option via serializer I2C commands. 

    2. Display touch screen need to enable by same I2C communication.

    Kindly let us know the I2C configuration for PWM generation and touch enable on de-serializer side.  

    Thanks,

    Boopathi.M

  • 0 in reply to Boopathi M
    TI__Mastermind 22946 points

    Hi Boopathi,

    Note that the frequency range has limitation with I2S. We highly recommend using the GPIO pins for PWM signals. Please see this E2E thread regarding your issue: (Link) Also, please refer to these app notes for your reference. (Utilizing Unused Pins as GPIOs in DS90UB925 and DS90UB926 & Using the I2S Audio Interface of DS90Ux92x FPD-Link III Devices)

    Best,

    Josh