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TCAN1146-Q1: Global Fault Flag work principle

Wenting Wu
Intellectual 2485 points

Part Number: TCAN1146-Q1

Hello Expert, 

In TCAN1146-Q1 datasheet, there is a description on datasheet that there is a global fault flag on a failing edge of nCS. May I ask about more work principle of it?

One of my customers has observed an spike on SDO signal when nCS turns to low level. We are not sure whether this spike is global fault flag. The voltage level of this spike is about 1.4V. We are worry whether it can cause wrong intterupt.

Best regards,

wenting 

  • +1
    TI__Guru 74302 points

    Wenting,

    This looks like just noise coupling from the nCS pin going back to high, not any real communication. Whether or not it will be interpreted as a communication bit will depend on the thresholds of your MCU. 7My assumption is that this is too low to be seen as a real bit, with 3.3V logic thresholds, I think this will be okay, but again, it depends on the threshold specification of the MCU. 

    The coupling may be due to layout, typically I don't see this much of a voltage spike on SDO when nCS is transitioning high-to-low.

    Regards,

    Eric Hackett 

  • 0 in reply to Eric Hackett
    TI__Intellectual 2485 points

    Hello Eric,

    Thanks for your explanation. May I ask if the global fault flag works, what will be the waveform look like? I can not find any more details on it in the datesheet, do you mind helping to give more information about?

  • 0 in reply to Wenting Wu
    TI__Guru 74302 points

    Wenting,

    The Global fault values will look like typical SPI waveforms, because they are part of the SDO return message when the TCAN1146-Q1 is addressed by the MCU. 

    Regards,

    Eric Hackett 

  • 0 in reply to Eric Hackett
    TI__Intellectual 2485 points

    Hello Eric, 

    I've forward the schematic and layout for you through email. The spike issue still exists. Do you mind having a view on it? if possible, when you come back from holidays, the customer wants to have a WEBEX meeting with you to discuss the issue.

    Best regards,

    Wenting

  • 0 in reply to Eric Hackett
    TI__Intellectual 2485 points

    Eric,

    May I  also ask does nCS and SDO have relationship refer to their integrated circuit design?

    The spike of SDO in previous posted picture seems like not caused by coupling but the working principle of TCAN1146-Q1. 

    if the spike can not be canceled. Do you mind helping to evaluate its risk?

    Best regards,

    wenting 

  • 0 in reply to Wenting Wu
    TI__Guru 74302 points

    Wenting,

    When nCS for the particular device is active, then the rest of the SPI signals (SDO, SDI, SCLK) also become active. As you can see in your waveform, the initial spike occurs when nCS goes active, so SDO is going from high-impedance to active at that point, and then immediately being driven low. This would indicate some kind of inherent timing difference, but I haven't seen this occur in other customer's designs.

    All of that being said, since the spike is never close to an output high threshold for the actual SDO waveform, this is little to no risk for the application. The receiving device won't misinterpret this as a high.

    Regards,

    Eric Hackett 

  • 0 in reply to Eric Hackett
    TI__Intellectual 2485 points

    Hello Eric,

    Thanks for your clear explanation. Do you have a regular waveform of nCS, SDI and SCLK? My customer wants to compare with it. 

    Can the nCS keep low all the times?

    May I also ask for the code drive of TCAN1146-Q1?

    Best regards,

    wenting 

  • 0 in reply to Wenting Wu
    TI__Guru 74302 points

    Wenting,

    Let me look to see if we have any examples and get back to you tomorrow.

    nCS can't stay low permanently, it will go active for every SPI transition and then transition back high automatically once the transaction is completed.

    If you email me directly at e-hackett@ti.com I can send over the driver code.

    Regards,

    Eric Hackett