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DP83TC813R-Q1: [STLA]: Eth Phy Registers

Mostafa Kandeel
Prodigy 141 points
Part Number: DP83TC813R-Q1

Hello All,

The topic is about reading EthPhy Registers: TX_PKT_CNT, RX_PKT_CNT and especially RX_PKT_CNT_3

I have a couple of questions that would appreciate answers for them:

1- What is the proper way to read the registers TX_PKT_CNT_3 and RX_PKT_CNT_3?

2- There was a trial to read the registers RX_PKT_CNT_1 (0x063C)and RX_PKT_CNT_2 (0x063D) with the procedure of reading external registers 
                   Step 1) write 0x1F to register 0xD
                   Step 2) write 0x063C to register 0xE
                   Step 3) write 0x401F to register 0xD
                   Step 4) read register 0xE

 if I read the register again the register seems to reset and start from 0 again, as the screenshot attached shows the printed result from reading the RX_PKT_CNT_1 register.
What could be the reason of such response?

3- Could you provide an example on how to inject error on the Ethernet bus that would reflect in the registers RX_PKT_CNT_3 (0x063E) whether on HW or SW level?

and Thanks in advance

Best regards

  • 0
    Expert 2988 points

    Could you please help us regarding this topic (assigning it to the proper team)? 

    CC: ,

  • 0
    TI__Expert 4740 points

    Hello Mostafa, 

    1. Yes the trial you mention in point 2 is the correct way of reading the registers TX_PKT_CNT, RX_PKT_CNT. 

    2. The reason for this response is because this registered is supposed to be cleared when registers 0x63C, 0x63D, 0x63E are read in sequence. 

    3. Some examples you can try to inject error on the ethernet bus is injecting error from the MAC, as well as skewing the timing from the MAC heavily to induce error. 

    Regards,

    Avtar 

  • 0 in reply to Avtar Dhaliwal
    Prodigy 141 points

    Hello Avtar

    Thank you for your response, But I want to ask regarding point 2 and point 3 in more details.

    For Point 2: On our side of Implementing EthTrcv, we actually do not read the registers 0x63C, 0x63D or 0x63E at all, so I still don't know why the registers are cleared

    For Point 3: for example if I would skew the timing from the MAC, this would be by configuring the timing from the MAC in the PHY chip? and which would be the configuration that would need to be manipulated?

    Point 1 is finalized for me

    Appreciate your fast response.
    Thanks in advance

    Regards,

    Mostafa Kandeel

  • +1 in reply to Mostafa Kandeel
    TI__Expert 4740 points

    Hello Mostafa,

    For Point 2: I am confused in your initial post I see that the screenshot posted has the result of reading the RX_PKT_CNT_1 register which is 0x063C. The registers will be cleared upon read. 

    For Point 3: Skewing timing of the MAC from the MAC side not in the PHY chip, so the timing inside the MAC sending to the PHY you can skew heavily so that when it reaches the PHY the setup time will be grossly off inducing the error needed. 

    Let me know if you have any further questions as well as if my point 2 doesnt make sense. 

    Regards,
    Avtar 

  • 0 in reply to Avtar Dhaliwal
    Prodigy 141 points

    Hello Avtar

    Okay, thank you for your fair explanation of the points, this solves the issue for me.

    All the points are fixed for me now.

    Have a nice day.

    Regards,
    Mostafa Kandeel