DP83826E: difference between hardware revision 0 and 1

Hi Sven,

The only different between revision 0 and revision1 on DP83826E is the internal strap resistor of the pin. If possible, could you double check on the strap resistor and see if you are seeing the right strap mode between Revision 0 and Revision 1?

The strap register is 0x0467.

May I also confirm one more time all the schematic are the same between two boards right?

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Regards,

Hillman Lin

Hello Hillman,

thank you for your quick response.
The schematic for both boards is the same. The only difference is the revison of the DP83826E.

We just read the strap register. The value is the same for both revisions: 0x0086 corresponding to the settings in the schematics. But we discovered that the revision 0 starts up as 10Mbit/s halfduplex instead of the wanted 100Mbit/s full duplex. We now initalised the chip to 100Mbit/s full duplex in software. Checking the registers showed that this worked correct. When sending an ethernet frame from another ECU, the revision 0 looses the link and jumps to 10Mbit/s halfduplex. It recovers automatically to 100Mbit/s full duplex after some seconds, but fails again when we send the next frame...

The revision 1 chip doesn't show this behavior.

Regards

Sven

Hi Sven,

Thank you for sharing the observation. It seems like it is an signal quality issue that is making the PHY drop the speed. If possible, could you read register 0x0218 for both of the register and provide a register dump for Register 0x0000 to 0x001F for both Revision 0 and Revision 1 PHY?

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Regards,

Hillman Lin

Hello Hillman,

I just read out all registers you asked for (see below) directly after startup before starting communication. For the rev 0 chip I read the registers with our standard initialisation we use for rev 1, which worked there without any problems, and with additional setting of the registers 0x00 and 0x04 as shown below:

If it is a signal quality issue, why is it working with the rev 1 chip and why does the rev 0 shows totaly different values right after startup?

How can we distinguish these two revisions by their ordering number for future PCBs?
Where in the datasheet are the differences between these two revisions described?

Regards

Sven

Hi Sven,

Between rev1 and rev0, it is mainly changes on the strapping option. In revision 1, we also have enhanced mode for EtherCAT application. From the register read on 0x000A and 0x000B, I did see that your odd nibble detection is enable which is will always bring unexpected issue on EtherCAT application. 

If possible, could you also change the register 0x000A and 0x000B to see if that help with your application.

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Regards,

Hillman Lin 

Hello Hillman,

we just tested it with register 0x0A set to 0x102 and register 0x0B to 0x09. These are the values which are working in rev 1. There is still no communication with the rev0 chip possible.

Please provied us an errata sheet and a detailed description of the differences between rev 0 and rev 1 and a workaround to get rev 0 working.

Regards

Sven

Hi Sven,

Could you ask FAE to send me a message? I can share the documentation through the email but those information is under NDA which require send those information through the email.

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Regards,

Hillman Lin