Power over Data Line - PD Design Application Note SNVAA25A

Marc Starkl

Hello,

I have a question regarding Figure 3-8 (PSE start-up Behaviour) in the Application Note SNVAA25A (IEEE 802.3cg 10BASE-T1L Power over Data Lines Powered Device Design).
According to the figure tje PSE output current rises above the prebias valid criteria (= current consumption between 1.25mA and 1.85mA) after the prebias gets enabled.
But after approx. 3ms the current consumption decreases and meets the prebias valid criteria (see yellow rectangle). How is this step implemented?

over 2 years ago

+1 David Creger over 2 years ago

TI__Mastermind 27662 points

Hi Marc,

I will need to check with the team on this. As it is holiday season I will need some time and will get back as soon as possible.

Thanks,

David

0 Hillman Lin over 2 years ago in reply to David Creger

TI__Mastermind 26035 points

Hi Marc,

The reason why we have a period of time before it properly reach prebias valid stage because it is charging the caps on the PD boards to turn on the MCU on the PD boards. After caps is fully charge, the idle current will drop to around 1.5mA which trigger the prebias stage in PSE board.

Regards,

Hillman Lin

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Power over Data Line - PD Design Application Note SNVAA25A