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PCA9548A: How does the level shift towards the downstream side work?

Part Number: PCA9548A


For an application where one master access 8 slaves/sensors, I have designed in the PCA9548APW I2C switch. 

Our master will use 3.0V or 3.3V, but the slaves will have 2.5V supply.

When reading the datasheet, I got a little confused regarding the term "clamp the downstream bus voltages". 

I assume that the output towards the downstream side is not really clamped!?

To be able to pull-up to the voltage used at the downstream side, I would expect there should be some kind of level shift?

Ex. an N-ch. mosfet level shifter with the "clamped voltage" at the source/gate side, and the drain side towards the output pin. Is this correct?