We need to connect 8 lines 1Gbps ETHERNET (SFP) through a 10 Gbps Fiber link.
We have choosen TLK10081 for this.
Is it posssible to get a full configuration for this. We have tested many configuration of HS/LS, PLL/VCO ...
CLK_0 and CLK_1 are 10ppm TCXO (both side). CLK_0 is 125 MHZ, CLK_1 is 156.20 MHz.
It works with loopback (with fiber), but 8B/10B errors appear with fiber link (2 boards).
Best regards.
Hi Raul,
I work with Gilles in the same project and I‘m testing the SERDES tlk10081. I’d like to know if this component can serialize 8 giga ethernet 1000 Base-T links using RJ45 SFP modules (instead of 1G 1000 BASE-LX SFP). If so, which mode could I use: 8b10b mode or bit interleave?
What data rates does your application require on the HS side and the LS side per channel? I'm unsure which interleaving method is better suited for your application, as it depends on how you would like data from the LS channels to be combined into the HS channel. If world interleaving is chosen, the low speed data streams are interleaved in a round-robin fashion 10 bits at a time. If bit interleaving is chosen, the interleaving is performed on a bit-by-bit basis.
I'm a little confused about what tests have been performed and what the results were. Can you confirm that the following block diagrams and results are correct, as well as answer my questions?
1. Fiber loopback test: passed
My assumption of how this test was performed: The computer transmits PRBS data on the 8 LS channels, then checks for errors on the received 8 LS channels. The computer didn't see any errors, so the test passed. Please correct me if I am wrong about any details here.
2. FPGA link test: passed
You mentioned the first FPGA is transmitting 8b/10b encoded 16-bit words. I'm assuming this test passed because the second FPGA receives this data correctly without any errors.
3. Ethernet link test: failed
You mentioned this test failed because the computer was not able to communicate with other computers on the LAN.
I am still reviewing your register dump, and will plan on sharing my comments by EOD 1/24.
Best,
Lucas
Hi Lucas,
Thanks you for your quick response. Below some clarifications :
I have 2 tlk10081 and 2 FPGA
REF FREQ = 156.25 MHz, LS in 1.25G ans HS 10G
Each FPGA has a GTH interface configured in 1.25G, coding 8b10b, word of 16 bits and 2 bits ctrl
1.- Test passed:
FPGA (sfp) ---- fiber ------(sfp)[tlk10081](sfp 10G) ----fiber-----(sfp 10G)[tlk10081](sfp) ----fiber-----(sfp 1.25G) FPGA
Using only SFP 1.25G for the LS channels and SFP 10G for the HS ones.
Each tlk10081 is configured in 8b10b mode, lanes in 1.25G and HS in 10G.
I send and receive data without problems. Data sent is just a incrementing value from 0 to 511.
2.- Test Failed :
FPGA (sfp RJ45) ----eth cable------(sfp RJ45)[tlk10081](sfp 10G) ----fiber-----(sfp 10G)[tlk10081](sfp RJ45) ----eth cable-----(sfp RJ45) FPGA
With the same configuration, I only changed the SPF 1.25G for SFP RJ45 and the fibers for ethernet cables on the LS side
3.- Test failed :
computer (RJ45) ----eth cable------(sfp RJ45)[tlk10081](sfp 10G) ----fiber-----(sfp 10G)[tlk10081](sfp RJ45) ----eth cable-----(RJ45) Switch LAN
With the 2 modes (8b10 and bit interleaved)
To configure the 2 tlk10081 modules in bit interleave I use this configuration: I use a bash script to write registers.
./write_mdio $eslave 0x00 0x8610 # are applied to both HS 0/1 macros
# reset with bit15=1
./write_mdio $eslave 0x01 0x0302 # disable link training|interleaved EN
./write_mdio $eslave 0x02 0x831B # HS CLKREF 156MHz PLL=x16
./write_mdio $eslave 0x03 0xA848 # HS
./write_mdio $eslave 0x06 0x8114 # LS, select lane 0 CLKREF 156MHz PLL=x8
./write_mdio $eslave 0x07 0xDD05 # LS_serdes control 2
./write_mdio $eslave 0x0A 0x3400
./write_mdio $eslave 0x0B 0x3700 #pattern PRBS 2^31 -1
./write_mdio $eslave 0x17 0x0ABC
./write_ind_mdio.sh $eslave 0x8009 0xFC00
./write_ind_mdio.sh $eslave 0x8019 0xFC00
./write_mdio $eslave 0x1C 0x0300 # disable RX et TX GIGe
./write_mdio $eslave 0x1D 0x0880
./write_mdio $eslave 0x0E 0x0008 # reset path
I tried changing these registers:
#./write_mdio $eslave 0x1C 0x030E # enable RX et TX GIGe|BYPASS
0x1C 0x030E
0x01 0x0000 also with success
Best regards,
Raul
