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TIC12400-Q1: IN20~IN23 always read "0"

Part Number: TIC12400-Q1

Hi, Support Team

There’s a problem about TIC12400-Q1 chipset register control, the detail as

.When Configure the chipset all input pin to comparator mode (Digital switch), the IN20 ~ IN23 can’t detect the state.

        .The register configure sequence follow application note(“Application note_scpa056.pdf”) page 4.

Could you help to confirm which configuration wrong makes the IN20 ~ IN23 can't detect state, and the register config information as:

         > IN_EN:          0xFFFFFF

         > CS_SELECT:      0x000000

         > WC_CFG0:       0x6DB6DB

         > WC_CFG1:       0xDB6DB

         > MODE:          0x000000

         > CONFIG:         0x000566  (CONFIG-POLL_EN/POLL_TIME/ POLL_ACT_TIME)

         > THRES_COMP:    0x000555

         > CONFIG:         0x000D66  (CONFIG-TRIGGER)

         > INT_EN_COMP1:  0xFFFFFF

         > INT_EN_COMP2:  0xFFFFFF

> INT_EN_CFG0:    0x000004

> INT_EN_CFG1:    0xFFFFFF

> INT_EN_CFG2:    0xCCCCCC

> INT_EN_CFG3:    0x0C30C3

> INT_EN_CFG4:    0x00030C

Please note:  IN20~IN23 no load, measurement is low level, connect to GND or High, through SPI command read always is "0"

if any suggestion, Please advise me.

Thanks,

Best regards,

Lawrence

  • Hi Application team :  

       I would like Supplementary explanation from Laurence IN0~IN19 can detect "High level" and can get "low level" when switch to GND. but still cannot detect any level from IN20~IN23 with using same register coding flow . could you give more debugging information ? thank you 

    Roy 

  • Hi Application team ,:

       do you have any suggestions? 

    thank you 

    Roy

  • Hi Lawrence and Roy,

    Thank you for your patience for the delayed response due to the Holidays.

    From your register configuration sequence, you should not be setting the Trigger Bit in the CONFIG register until after you have configured the INT_EN_COMPx and INT_EN_CFGx registers.  Once the Trigger bit is set, the device should be fully configured and it will start it's polling sequence.  If you writing to the INT_EN_xxxx registers after the TRIGGER bit is set, these registers will not take the new value.

    However, the INT_STAT_COMP should still reflect the INx pin state because the thresholds and wetting current settings were configured while TRIGGER = 0.

    What is the resistance of the switch or load not shown in the schematic for the IN20-IN23 pins?  For example, is it a direct connection to GND with <100 ohms of resistance?  Are the switches/loads the same for IN0-IN19 inputs?

    Have you looked at the IN20-IN23 pins with a scope to see what the voltage levels are during the polling state?  It could be that the switch/load resistance or wetting current settings are not compatible with the 2.7V comparator threshold. 

    Please try configuring different comparator thresholds and wetting current levels to see if there is a point where a switch state is detected. Also please provide any scope plots and additional information about the switches used for this testing and how they are connected with the schematic already provided.

    Thanks and Regards,

    Jonathan

  • Hi Jonathan:

       Thank you very much your support , customer issue has been fixed. thank you 

    Roy

  • Hi Roy,

    Thank you for letting me know this issue has been resolved.

    Regards,

    Jonathan