Our design includes a gigabit PoE ethernet interface based around the DP83867 PHY, and we're currently unable to establish a network link of any kind. We have confirmed that we are able to communicate with the PHY and read its configuration registers from our MPU. Below is our schematic.
The PHY datasheet discusses requirements for the magnetics and mentions that the center taps on the PHY side must all be isolated and individually bypassed with 0.1 uF capacitors. The RJ45 jack we have chosen does not bring these center taps out individually and instead busses them all together, so we are thinking this may be the culprit here. But I was hoping for some clarification on this because it's hard to see how bussing these center taps would affect the differential signals going in and out of the PHY.
Here's the excerpt from the PHY datasheet: