• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 257 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UH947-Q1: 947-948 GPIO mapping latency

Roy Chou1
Genius 16210 points
Part Number: DS90UH947-Q1

Hi Team,

How can we calculate the estimated delay time for GPIO mapping. (Both of FC and BC)

Condition :

FPD3 single lane

PCLK : 50MHz

Backward channel : 20Mbps

Regards,

Roy

  • 0
    TI__Mastermind 34185 points

    Hi Roy,

    How many GPIOs will be sent over for forward and back channel?

    The equation for forward channel GPIO latency is: 35 [bits/frame] / FPD-Link rate [bits/second]. For your case the forward channel GPIO latency would nominally be 20ns.

    The worst case back-channel GPIO latency can be defined as: BC_Delay (Worst Case) = 30 [bits/frame] / BC frequency [bits/sec] * 2. For your case the back channel worst case GPIO latency would be 3µs. Nominal latency would be 1.5µs. The back channel frequency can have up to the 20% frequency variation.

    Best,

    Jack