DP83TC812R-Q1: Does DP83TC812R support tx/tx internal delay adjusted by software register?

Part Number: DP83TC812R-Q1

Hi, TI Expert.

As title description, we already know DP83TC812R support "RGMII tx/rx internal" delay base on different "hardware bootstrap pin" setting.

Question 1 : Could we also change "RGMII tx/rx internal" by register setting without bootstrap pin? (y/n)

If the answer is "yes", and then "How to do it"?

Question 2 : Does register A2D_REG_48 (Address = 0x430h) do an additional setting for "RGMII tx/rx internal"? (y/n)

I must make sure "RGMII tx/rx internal" work, and then "A2D_REG_48" works, Is it right?(y/n)

CLK shift 90 degree, the default value should be 111b.

Question 3: Need sample code to access  A2D_REG_48.

Already download code here, and try to modify some bug base on these two link.

https://git.ti.com/gitweb?p=ti-analog-linux-kernel/analog-linux.git;a=blob;f=drivers/net/phy/dp83tc812.c;h=0c594375f188d40299603628a0636947cfea35bf;hb=f973f3deb81b1f44aa4c33b275a342e28fc982fd

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1271678/dp83tc812s-q1-validation-of-sgmii-failed?tisearch=e2e-sitesearch&keymatch=LM5050-1-Q1

We found these driver do not support A2D_REG_48 setting, Could you give us some example?

Many Thanks

Gibbs