This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83848I: 10/100Mbps About

Part Number: DP83848I
Other Parts Discussed in Thread: DP83826EVM

Hello.

I have a question about the DP83848 Auto-Negotiation feature.

I've configured the circuit as shown in the attached picture, and I'm wondering if it is set up correctly for 10BASE-T, Half/Full-Duplex, 100BASE-T, Half/Full-Duplex.

Additionally, is it correct that the AN_EN, AN1, AN0 pins can be left floating while still using 10BASE-T, Half/Full-Duplex, 100BASE-T, Half/Full-Duplex?

  • Hello,

    From what I am seeing, you have the PHY strapped into force 10Base-T Half Duplex mode due to pins 26-8 being default. This is due to when the PHY samples its straps, there is no way for a '1' voltage to reach the pin at the time as the diode and current limiting resistor will absorb most of the voltage. In order to strap this pin high, please attach a PU resistor in parallel to each pin such that there is straight pathway to VCC. Please see DP83826EVM schematic for examples of this parallel circuit.

    Sincerely,

    Gerome