Hello,
We use the tmds1204 between the HDMI connector and the FPGA.
We have determined the following best parameters for acquiring sources up to 40Gbps
i2cset -y 14 0x5c 0x11 0x00
i2cset -y 14 0x5c 0x0a 0x40
i2cset -y 14 0x5c 0x0b 0x23
i2cset -y 14 0x5c 0x0c 0x00
i2cset -y 14 0x5c 0x0d 0x42
i2cset -y 14 0x5c 0x0e 0x97
i2cset -y 14 0x5c 0x12 3
i2cset -y 14 0x5c 0x13 14
i2cset -y 14 0x5c 0x14 3
i2cset -y 14 0x5c 0x15 14
i2cset -y 14 0x5c 0x16 3
i2cset -y 14 0x5c 0x17 14
i2cset -y 14 0x5c 0x18 3
i2cset -y 14 0x5c 0x19 14
i2cset -y 14 0x5c 0x31 0x34
i2cset -y 14 0x5c 0x09 0x00
i2cset -y 14 0x5c 0x11 0x5f
Unfortunately the video signal inside the FPGA jitches a lot despite the adjustments of all the parameters in the FPGA part (seen with Intel) and the PCB manufacturing and routing seem to be correct (QSFP+ works correctly on the same PCB @10G per lane), and we think it may be a problem of parameter setting on the TMDS1204 side.
According to the TMDS settings above, do you think we've missed something? Or is it not configured correctly?
Why do we have to reconfig the tmds12
Best regards,
Khalid
