TFP410: recommendation for termination if no-pop

Hey Kieth,

I'm looking into this and will have a response ready next week. Due to national holiday my response will be slightly delayed. Sorry about that

Hello and Thank you!   We have a couple more quesitons:

When using manual configuration of the TFP410, I2C/RST low, can the design be configured to disable the T.M.D.S transmitters when no monitor is connected and re-enable with the monitor is connected?

Example:

• I2C/RST Low (using external configuration pins)
• MSEN/PO1 pin tied to /PD pin.
• The MSEN/PO1 pin will be High when a monitor is detected and Low when a monitor is not detected.
• The /PD pin places the chip in power down mode Digital I/O buffers remain active.
• In the example above, when /PD is low, will the MSEN/PO1 monitor detection circuitry function and drive MSEN/PO1 pin accordingly?
• When using manual configuration of the TFP410, I2C/RST low, can the design be configured to disable the T.M.D.S transmitters when no monitor is connected and re-enable with the monitor is connected?

Also the TFP410 can be configured to work with different CMOS input standards (1.1V to 1.8V) by configuring the voltage level on VREF.  If 1.8V CMOS standard is used, the VREF shall be configured to ½ 1.8V which is 0.9V. 

• The VREF pin has recommended operation voltage max of 0.9V.
• If configured for 1.8V standard is VREF = 0.9V the correct setting?
• The tolerance for 1.8V will be 5% and VREF would go to  0.945V, is this acceptable for the VREF input?
• Which CMOS inputs will be referenced to VREF / 2?

Very much appreciated, Keith

The best way to see if you can use the hot plug to power down/ on the device would be use a test setup like the following block diagram. 

Keep in mind that MSEN is pulled low when a monitor is detected and high when a monitor is not detected. This means that you will need to invert the signal between PD and MSEN as when PD is low the device will be in power down mode. If a signal is seen on the scope when MSEN is low, then you can move forward with testing with the proper display. 

The Vref will set the following pins' voltage swing:

I would recommend not going over the recommended 0.9V maximum. Is it possible for you to reduce your voltage swing for the pins that are set by Vref, or simply use the full 3.3V?

FYI

Hi Vishesh,

MSEN had a correction via the Errata document, SLLZ030A–June 2003–Revised April 2009, Which is correct?

The Datasheet indicates the TFP410 supports interface standards: 1.1 to 1.8 and 3.3 CMOS input levels. The CMOS input is configured via the VREF pin. The SLLA152 – SEPTEMBER 2003 DVI on the Motherboard Using the TFP410, indicates 1k resistors are used to configure the low-swing. The Datasheet also references low-swing mode and indicates VREF must be 0.55 to 0.95V in the text and then states the range 0.55 to 0.90 within the same section of the datasheet. 0.95 would be correct for 1.8V standard. What is the recommendation for 1.8V logic level configuration?

Your input very much appreciated, Jim

Hey Jim,

I'm consulting the owner of the datasheet for more accurate values. It seems that this devices reference documents are inconsistent. Ill let you know as soon as I have an answer.

Hi Vishesh,

Thanks for the info.  Can we use 10K pull-ups versus 1K?

Vref is 1K and 1K to get to 0.9V.  Could we reduce the power requirement be going to 10K?

Thank you, Keith