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SN65LV1023A: Random-Lock Synchronization mode

Shuji Ishiwata
Mastermind 8100 points
Part Number: SN65LV1023A
Other Parts Discussed in Thread: SN65LV1224B,

Hi All,

I have a question about SN65LV1023A and SN65LV1224B.

1) Is it correct to understand that Random-Lock Synchronization mode has a slower locking time than Rapid Synchronization mode, but it is automatically locked?
2) Please tell me how to set it to Random-Lock Synchronization mode. Do you want to pull down the SYNC1 and SYNC2 pins?
3) Do you have any datasheet or pin assignment materials for SN65LV1224B? I could only find SN65LV1023A.

Best Regards,
Ishiwata

  • 0
    TI__Guru* 76991 points

    Hi Ishiwata,

    I'll try to get you a reply by the end of this week. Sorry for the delay.

    -Bobby

  • 0
    TI__Guru* 76991 points

    Hi Ishiwata,

    Sorry for the delay in response. I had to connect with one of my colleagues about this part since it has transitioned into a new group at TI (from the translation product line within TI to the transceiver product line in TI).

    Shuji Ishiwata said:
    1) Is it correct to understand that Random-Lock Synchronization mode has a slower locking time than Rapid Synchronization mode, but it is automatically locked?

    ~kind of. The 'lock' still requires both reference clocks to be within 100ppm of each other. If the Rapid Synchronization mode is used and both clocks are similar to each other then the lock should be automatic (requires the 1026 cycles stated in the datasheet).

    Shuji Ishiwata said:
    2) Please tell me how to set it to Random-Lock Synchronization mode. Do you want to pull down the SYNC1 and SYNC2 pins?

    The Random-Lock Synchronization mode does not use the SYNC1/SYNC2 pins. They should be held LOW if you want to use Random-Lock Sync Mode.

    Shuji Ishiwata said:
    3) Do you have any datasheet or pin assignment materials for SN65LV1224B? I could only find SN65LV1023A.

    This should be page 6 of the datasheet under the Row called 'DESERIALIZER'

    The first Column is for the DB package and the second Column is for the RHB package.

    -Bobby

  • 0 in reply to BOBBY
    Mastermind 8100 points

    Hi Bobby,


    Thank you for your answer.

    What does " ~kind of. " mean in your answer?

    Random-Lock Synchronization mode is understand to be automatically locked.
    Also, do I need to pull down both SYNC1 and SYNC2 when setting random lock synchronization mode? Will it be set to random lock synchronous mode even if I pull down only one side?

    I understand that there is no diagram for SN65LV1224B like the SN65LV1023A below, is this correct?


    Best Regards,
    Ishiwata

  • 0 in reply to Shuji Ishiwata
    Mastermind 8100 points

    Hi Bobby,

    I have been waiting for your reply, but have not heard from you.
    Could you give us a response?

    Best Regards,
    Ishiwata

  • 0 in reply to Shuji Ishiwata
    TI__Guru* 76991 points
    Shuji Ishiwata said:
    I have been waiting for your reply, but have not heard from you.
    Could you give us a response?

    Sorry, I was out of the office yesterday.

    Shuji Ishiwata said:
    What does " ~kind of. " mean in your answer?

    If the two clocks are not within 100ppm  of each other, even if you use rapid sync mode the devices may not sync with each other. I expanded on my ~kind of answer by emphasizing the importance of the two clocks being within 100 ppm. In my opinion, the rapid sync mode is better to ensure a positive lock occurs. When you use random sync mode, there is a possibility of a false lock occurring. Using random sync mode, you could get false positive locks which could occur earlier than 1026 cycles. 

    Shuji Ishiwata said:
    Also, do I need to pull down both SYNC1 and SYNC2 when setting random lock synchronization mode? Will it be set to random lock synchronous mode even if I pull down only one side?

    Both SYNC1 and SYNC2 need to be held to GND to use random lock synchronization mode. If one of the pins (SYNC1 or SYNC2) is held high for 6 clock pulses, then the device will try to synchronize using rapid sync mode. 

    Shuji Ishiwata said:
    I understand that there is no diagram for SN65LV1224B like the SN65LV1023A below, is this correct?

    Correct, the datasheet doesn't have the diagrams for the deserializer but the pinout is provided on page 6.

    Again, sorry for the delayed response.

    -Bobby

  • 0 in reply to BOBBY
    Mastermind 8100 points

    Hi Bobby,

    Thank you for your answer.

    I have an additional question.
    Should the input frequency to the deserializer's REFCLK be the same as the serializer's TCLK?

    Best Regards,
    Ishiwata

  • 0 in reply to Shuji Ishiwata
    TI__Guru* 76991 points

    Hi Ishiwata,

    Shuji Ishiwata said:
    Should the input frequency to the deserializer's REFCLK be the same as the serializer's TCLK?

    Yes, the Serializer's TCLK and the Deserializer's REFCLK should be within +/-100 ppm of each other.

    -Bobby