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TLK10002: TLK10002 application question

Part Number: TLK10002

Hi team,

could you help with below questions?

  1. Does the PRBS Generator in this device rely on external signal input? If the data or clock signal is input at the RX end, the PRBS code stream can be sent at the TX end.
    If the PRBS Generator does not rely on external signal input, how to adjust the PRBS stream rate?
  2. If the device need to enable the PRBS function, do you only need to configure registers B.7:6 and B.13:12 through MDIO and pull the PRBSEN pin high?
  • Hi Dane,

    Does the PRBS Generator in this device rely on external signal input? If the data or clock signal is input at the RX end, the PRBS code stream can be sent at the TX end.

    An external input signal is not required to use the PRBS generator.

    If the PRBS Generator does not rely on external signal input, how to adjust the PRBS stream rate?

    The data rate is determined by reference clock frequency and SerDes PLL multiplier setting. Please refer to the "Line Rate, SERDES PLL Settings, and Reference Clock Selection" section of the datasheet.

    If the device need to enable the PRBS function, do you only need to configure registers B.7:6 and B.13:12 through MDIO and pull the PRBSEN pin high?

    It is not required to pull PRBSEN pin high if you are using MDIO register settings to configure the pattern generator. There are different register writes necessary to use the HS pattern generator versus the LS pattern generator.

    HS side:

    • 0x0B[10:8] to select pattern
    • 0x0B[13]=0b1 to enable pattern generator
    • 0x0B[12]=0b1 to enable pattern verifier, if needed
    • 0x10 to see HS error count, if pattern verifier is enabled

    LS side:

    • 0x0B[5:4] to select pattern
    • 0x0B[7]=0b1 to enable pattern generator
    • 0x0B[6]=0b1 to enable pattern verifier, if needed
    • 0x11, 0x12, 0x13, 0x14 to see LS error count on each lane, if pattern verifier is enabled

    Best,

    Lucas