SN65DPHY440SS: MIPI-DSI: Maximum lane flight time

Stefan Zoller

Part Number: SN65DPHY440SS

Hello team

I like to use a 500mm cable between the processor and the display. Using a high quality TwinAx cable from 3M the insertion loss is <5dB at the desired frequency and can be compensated by the SN65DPHY440SS. However the MIPI D-PHY specification V1.1 notes a maximal flight time of 2 ns that can obviously not be compensated.

Is the return channel of the display still functional even with the higher round trip time caused by the cable?

Considering the SN65DPHY440SS has a delay of >12 ns on it's own how can the chip be compliant with MIPI D-PHY V1.1 in the first place as it violates the flight time requirement?

Thanks for clarification

Best regards

Stefan

6 months ago

0 David (ASIC) Liu 6 months ago

TI__Guru**** 151420 points

Stefan

The DPHY440 does not care about the flight time, so the impact of having a flight time outside the spec comes down to the source and the sink.

Thanks

David

0 Stefan Zoller 6 months ago in reply to David (ASIC) Liu

Prodigy 20 points

Hi David

Thanks for the quick reply. I understand it always comes down to the specific source and sink, but as we may need to change the display over the lifetime of the product I need to be reasonably confident that the solution will work for most displays.

Researching some more I found this thread discussing the same topic: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/915756/sn75dphy440ss-does-the-d-phy-2nsec-limit-apply-to-the-output-side-independent-of-the-input-side

As I read it, the 2ns limit is for each individual link("source to redriver", "redriver to redriver", "redriver to sink") and not for for the total connection ("source to sink"). Therefore each SN65DPHY440SS can extend the link by 25cm and using multiple you could create in theory an arbitrarily long link. Is this correct?

Regards Stefan

+1 David (ASIC) Liu 6 months ago in reply to Stefan Zoller

TI__Guru**** 151420 points

Stefan

You can use multiple DPHY440 to extend the link. The length of the link depends on the insertion loss of the link being able compensated by the source TX/DPHY440 RX equalization and the DPHY440 TX/Sink RX equalization.

Thanks

David

0 Stefan Zoller 6 months ago in reply to David (ASIC) Liu

Prodigy 20 points

David
Thanks for the clarification.

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SN65DPHY440SS: MIPI-DSI: Maximum lane flight time