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SN75LVPE5412: TX and RX line lengths, as well as adjustment methods

HongXi Chiu
Prodigy 20 points
Part Number: SN75LVPE5412
Other Parts Discussed in Thread: SN75LVPE5421

Hello, I have encountered some issues with the SN75LVPE5412.

  1. May I inquire if there are Layout Guidelines specifically regarding the length of TX and RX lines?

  2. In the scenario where I am using Pin Mode, and there are no speed issues with Port A, but abnormalities occur when switching to Port B, how should I make adjustments?

  3. In the situation described in question 2, are there any specific requirements for the lengths of TX and RX lines?

  • +1
    TI__Mastermind 20901 points

    Hi HongXi,

    1. It is difficult to estimate the length requirements for TX and RX high-speed differential lines to the device, as this is dependent on board material, board stackup, routing, placement, etc. Please refer to the following application note for further details: https://www.ti.com/lit/an/snla426/snla426.pdf 
    2. Which EQ and GAIN settings are being used in Pin Mode for the device? The EQ settings for all channels are set using EQ0/1 and GAIN in Pin Mode. It is possible that a different EQ value is needed to accommodate for both scenarios.
    3. Please refer to my response in bullet #1.

    Best,
    David

  • 0 in reply to David Waier
    Prodigy 20 points

    Hello, I am currently using the SN75LVPE5412 and SN75LVPE5421 for PCIe Gen5 x16 conversion, either into a single PCIe Gen5 x16 or two PCIe Gen5 x8 configurations.

    There are two proposed layouts for the IC positions, as shown in options A and B, along with associated trace lengths.

    Could you please advise whether it is recommended to proceed with option A or option B? Additionally, are there any other suggestions?

    Thank you!

  • 0 in reply to HongXi Chiu
    TI__Mastermind 20901 points

    Hi HongXi,

    Both options appear that they could be feasible. Please note that TI provides an IBIS-AMI model for this device for simulation with your modeled traces, connectors, etc., as well as the EVM layout BRD file for reference. I have granted your myTI account access to these documents for reference.

    Best,
    David

  • 0 in reply to David Waier
    Prodigy 20 points

    Hi David Waier

    1. If both options are feasible, is there a preferred recommendation between the two?

    2. Regarding the 1 inch mentioned in the diagram, does it refer to the allowable difference within 1 inch from the Redriver output to the PCIe slot?

    3. For the IBIS-AMI model you mentioned, should I send an email to highspeed_models@list.ti.com to request access?

      Thank you!

  • +1 in reply to HongXi Chiu
    TI__Mastermind 20901 points

    Hi HongXi,

    1. It would be preferable to avoid unnecessary vias per the high speed pcb layout guidelines: https://www.ti.com/lit/an/snla426/snla426.pdf. However, modeling should be performed to simulate your environment with the device.
    2. I believe you are referring to Section 11 of the high speed pcb layout guidelines. This refers to the trace length difference between differential pairs (example: if Channel 1 is 3 inches long, Channel 2 should not be more than 1 inch less than or greater than Channel 1's (or any additional channel's) length.
    3. The secure resources folder I've granted you access to contains this IBIS-AMI model. Please find it by accessing your ti.com Secure Resources: 

    Best,
    David