This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPD3S713-Q1: ESD protection

Part Number: TPD3S713-Q1

Hi team,

I would like like to know the electrical parameter and ESD clamp waveform of ESD protection cell in TPD3S713-Q1 for DP/DM interface.

I connect DP/DM to SoC which has 1kV ESD tolerant and would like to know if TPD3S713-Q1 DP/DM ESD protection cell 

can clamp the voltage low enough for SoC I/O pin. 

regards,

  • Hi Tsuji-san,

    Sorry, I also can't find this data from our datasheet, but I find the DM_IN and DP_IN OVP threshold is about 3.9V typ. And short-to-battery test result, the DP_OUT go to about 5V. I guess the ESD test result should be similar, is it ok for you? Thank you. 

    Best Regards,

    Kuno