DS90UB928Q-Q1: DS90UB927QSQX/DS90UB928QSQX stripes appear when connected to camera(cameralink interface) and acquisition card

Hi Will,

Will liu said:

Symptom: In Full mode (clock frequency 85Mhz), the display appears vertical stripes (the content displayed is the content captured by the camera).

Is there a photo of the vertical stripes you can show? 

Will liu said:

Temporary solution: the problem does not recur after replacing the IC with 421/422;

What are the full part numbers for the 421 and 422? Are these TI products?

Because the camera is operating at the max operating frequency of 85 MHz, this will reduce the margin for LVDS frequency deviation. Are you able to run the camera at a rate lower than 85 MHz? 

Are you able to provide a register dump before the problem phenomenon and after the problem phenomenon. 

Best,

Jack

1.421 and 422 full part number is DS92LV0421SQ/DS92LV0422S which are producted by TI;

2.What's the different between DS92LV0421SQ/DS92LV0422S and DS90UB927QSQX/DS90UB928QSQX?

3.Because the camera is operating at the max operating frequency of 85 MHz, this will reduce the margin for LVDS frequency deviation. Are you able to run the camera at a rate lower than 85 MHz? --> We can't reduce the frequency.  How much allowance should be preserved for DS90UB927QSQX/DS90UB928QSQX? How much allowance should be preserved for DS92LV0421SQ/DS92LV0422S?  In this application scenario, is 421/422 more appropriate? 

Hello Will,

Will liu said:

What's the different between DS92LV0421SQ/DS92LV0422S and DS90UB927QSQX/DS90UB928QSQX?

These are two different device generations. The DS92LV devices do not support Back-channel communications. Also these do support lower max PCLK frequency (75MHz), hence I am confused how these are working better at 85MHz PCLK!

Will liu said:

Because the camera is operating at the max operating frequency of 85 MHz, this will reduce the margin for LVDS frequency deviation. Are you able to run the camera at a rate lower than 85 MHz? --> We can't reduce the frequency.  How much allowance should be preserved for DS90UB927QSQX/DS90UB928QSQX? How much allowance should be preserved for DS92LV0421SQ/DS92LV0422S?  In this application scenario, is 421/422 more appropriate? 

What type and length of cable are you using? 

Are you using the SSC function?

Hi Sir,

1. What type and length of cable are you using? ->10cm, normal cable;

2. Are you using the SSC function? No we haven't use SSC function;

3.In practical application,  421/422 PCLCK can support up to 85 MHZ， and work well;

question:

1. We haven't use the  Back-channel communications function ,  is this will effect the LVDS ?

    except that, is there any other differents?

2. Is there any way to try to adjust the DS90UB927QSQX/DS90UB928QSQX in order to solve the problem? Resistance, capacitance....etc？

below is the pic, please refer:

Hello Will,

Will liu said:

10cm, normal cable;

10cm may cause Signal Integrity issues. We recommend minimum 35cm.

What do you mean by normal cable?

Will liu said:

1. We haven't use the  Back-channel communications function ,  is this will effect the LVDS ?

    except that, is there any other differents?

As said, these are two different device generations, so almost everything is different, not only back channel.

Will liu said:

2. Is there any way to try to adjust the DS90UB927QSQX/DS90UB928QSQX in order to solve the problem? Resistance, capacitance....etc？

Please try a different cable type/ length. Also you may try with a lower PCLK than 85MHz.

Dear Sir,

    Is there any way to read the register contents of DS90UB927QSQX/DS90UB928QSQX ?

    Is it possible to find out  the problem by reading a change in the register, or by reading the contents of the register when the problem occurs?

Hi Will,

I am taking over this thread from Hamzeh.

Will liu said:

 Is there any way to read the register contents of DS90UB927QSQX/DS90UB928QSQX ?

There is an I2C interface that can be used to read the registers in the 927 and 928.

Will liu said:

3.In practical application,  421/422 PCLCK can support up to 85 MHZ， and work well;

The data sheet of the 421/422 lists a max PCLK of 75MHz. Even if these devices are able to work at 85MHz, this is outside of the recommended operating range.

Will liu said:

    Is it possible to find out  the problem by reading a change in the register, or by reading the contents of the register when the problem occurs?

Registers on the 927 to check are 0x0C (General Status), 0x0A and 0x0B (CRC Errors)

Registers on the 928 to check are 0x1C (General Status)

Further questions

• Are both the 927 and 928 following the recommended power-up sequence?
• Are EVMs used in this test or is this custom hardware?
• What is the status of the 928 lock pin during operation?

Best,

Jack

Hi Scherlag,

    Thanks for your reply.

 1.  About the regisisters

     If the register is  0x0A or 0x0B (CRC Errors) , how can I solve if?

    Which designs do I need to Check?

  2. It custom hardware.

  3. Are both the 927 and 928 following the recommended power-up sequence?

     Yes, both of them following the recommended power-up sequence.

  4. What is the status of the 928 lock pin during operation?

      The status of the lock pin is low.

Hi Will,

Will liu said:

4. What is the status of the 928 lock pin during operation?

      The status of the lock pin is low.

If the lock pin is low, there is a signal integrity issue preventing the 927 and 928 from communicating. The registers will not be useful if there is no lock between the devices.

Hamzeh Jaradat said:

10cm may cause Signal Integrity issues. We recommend minimum 35cm.

Can you swap out the 10cm cable for a different cable to test if lock is acquired. It is very important that these devices are locked during operation.

Best,

Jack

Hi Jack Scherlag,

    I see the data sheet write  as "An FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces medium-induced deterministic jitter. ".

  We found that the jitter was not good after the signal was transmitted over the cable. As this we want to try set the  adaptive equalizer to a Long Cable Mode (LCBL), using the MODE_SEL pin. -->In your mind , is it a way can be tried to solve this problem?

 When we set to LCBL mode,  what do we need to pay attention ? 

Can the AEQ be setted or it is seted automatically by regesiters that the AEQ is only canbe read?

The  Configuration Select as below:

One more thing，

      When vertical stripes occur, the phenomenon can persist and cannot be recovered。

Hi Jack Scherlag,

    Which is more tolerant of jitter than 928 or 422?

Hi Will,

For the channel length that this system is using, I don't think AEQ values for the LCBL mode will be useful. I suspect a grosser issue with the system.

Will liu said:

  We found that the jitter was not good after the signal was transmitted over the cable

How was this measurement done? Are you able to provide the data that was measured?

Can you send a picture of the setup and provide schematics for the 927/928? You can email this to j-scherlag@ti.com if you prefer to keep the schematics off of the forum.

Best,

Jack