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SN65MLVD040: Timing Characteristics

Part Number: SN65MLVD040


Hi,

I'm working on timing analysis that uses the SN65MLVD040 for transmitting CLK and Data. In the datasheet, it lists an Output skew and Pulse Skew for the MLVDS bus driver and receivers. Both of these parameters to me affect the time alignment of the rising and falling edges across the 4 channels. Is there a relationship between Output and Pulse skew? (ie does Output skew already include the Pulse skew?)

Thanks

  • Hi Jason,

    I'm going to talk to one of our system engineers for these devices to see if they can help me understand this. It looks like the datasheet doesn't show the definition/waveforms for these parameters. My interpretation of pulse skew is how much distortion/difference there can be between the rising edge vs the falling edge. I'm not sure what output skew is defining here though..

    -Bobby

  • Hi Jason,

    I spoke with the previous systems engineer and he stated the output skew is basically channel to channel skew between two channels of the same device. 

    Example: you apply the same input to 1A-B and 2A-B and see the output of 1R and 2R are not the same. 1R transitions faster than 2R by 50ps so 1R has a output skew of 50ps earlier than 2R in this example.

    -Bobby

  • Hi Bobby,

    If we assume DDR operation so the data is clocked in at both a rising and falling edge, would the worst case skew between 1R and 2R = Output Skew + Pulse Skew 1R + Pulse Skew 2R?

    -- Jason

  • Hi Jason,

    This seems to make sense to me. If we assume the clock is the 'true' signal and the data can vary/shift. Then the worst case for output skew is just the max value. Pulse skew worst case would be if one channel transitioned much sooner by the max value and the other transitioned much later by the max value (so pulse skew1 plus pulse skew2). 

    -Bobby