Hello, I am using the DS110DF111 on a custom PCB design to support a 10G Ethernet application between Ethernet controller (Intel XL710) to SFP+. I cannot get the CDR to lock on CH B. For my set-up, I have a 10G SFP+ AOC cable between a test station that has an SFP+ port to the SFP+ port on the custom PCB. I used SigCon Architect for debugging and to write to registers (I had to mainly write to 0x1F for both CH A and CHB to invert the the polarity of the output signals).
Please see attached for register values reads from SigCon Architect GUI. Are there any recommendations on how I can proceed with my troubleshooting?