Hi team,
For example, SCL/CFG0 and SDA/CFG1 is pulled high to external pull-up source 1.8V. During the EN=L, Is there no issue on the device? Could you let me know the internal block a bit more?
Best regards,
Hayashi
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Hi team,
For example, SCL/CFG0 and SDA/CFG1 is pulled high to external pull-up source 1.8V. During the EN=L, Is there no issue on the device? Could you let me know the internal block a bit more?
Best regards,
Hayashi
Hayashi,
There is no problem with I2C lines being pulled high while EN = L. However, the transactions on the I2C lane will be ignored until the EN = H.
Thanks,
Zach