DP83822I: RGMII settings in device driver

Hello,

If customer resets the PHY (either via pin of device or via Reg 0x1F = 0x8000), what does this value read? Also, which version of Linux are you using?

Sincerely,

Gerome

Hello,

When building petalinux without modifying the Dp83822 driver, the register value is 0x02C1.

Please refer to the link below for the Petalinux Kernel dp83822.c 

linux-xlnx/drivers/net/phy/dp83822.c at xlnx_rebase_v5.15_LTS_2022.1_update · Xilinx/linux-xlnx · GitHub

thank you

Hello,

I am a person who works with cho chanki.

If the value returned from PHY_GET_INTERNAL_DELAY is 0 or greater than 0, shouldn't I enable Transmit path internal clock shift?

Currently, DP83822.c disables when the value returned from PHY_GET_INTERNAL_DELAY is 0 or greater than 0.

If I enable that value, DP83822 will work properly.

We wonder whether that was what TI intended or not.

Hello,

There was a miss in the previous reply.

If the phy_get_internal delay function returns 0 or a negative, the code below sets the RGMII TX Clock Shift register value to 0.

and I think it is enable shift, not disable. In the datasheet, setting the value of the register to 0 is written enable.

why setting it to 0 is disable shift the function?

linux-xlnx/drivers/net/phy/dp83822.c at xlnx_rebase_v5.15_LTS_2022.1_update · Xilinx/linux-xlnx · GitHub

(from dp83822 datasheet)

Hello,

I understand you question now. I will need to check this with the team. Please give me until EoD tomorrow.

Sincerely,

Gerome

Hello,

Can you tell me what is going on for this issue?

Hello,

I apologize for the delay. I was checking with the team on this, and we came to a conclusion that the conditional may be flipped on this. 

If you change the TX_INT_DELAY conditional to > 0 instead of <= 0, would this resolve your issue?

Sincerely,

Gerome

Hello,

I changed code like this, and it works.