• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 346 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DSI83-Q1: Causes and solutions for occasional display screen blank issue

Krithika T
Prodigy 30 points
Part Number: SN65DSI83-Q1

Dear Expert,

We are working on a custom android based display device for our two-wheeler vehicle using SN65DSI83TPAPRQ1 enabled by SC200REMNB-E53-UGNDA. In general terms, our device works normally. However there is a very sporadic issue, the device screen goes blank. 0xE5 register holds value of 0X7d at 5th bit when this display blank occurs. We have to turn the vehicle key off/on for the display to turn back on. The config. registers of SN65DSI83TPAPRQ1 are reconfigured when key off/on is done. Can you help us with clearing this error.
Looking forward for your comments.
Thanks and Regards,
Krithika T
  • 0
    TI__Mastermind 23285 points

    It looks like the PLL unlocks causing all the other errors to trigger. This is most likely due to a jittery clock that the PLL cannot lock onto. What this the display panel spec ? and Are you using REF_CLK or the DSI_CLK?

  • 0 in reply to Vishesh Pithadiya
    Prodigy 30 points

    Thank you for the quick response,

    We are using DSI_CLK.A0700WXF2MAAADB01 Preliminary Spec V1.2 (1) (1).pdfConfig.reg values.pdf

    Attaching display panel spec and config. registers values.

  • 0 in reply to Krithika T
    TI__Mastermind 23285 points

    Hey Krithika,

    If possible try implementing a REF_CLK that meet the panel DClock Frequency of  62.23 MHz < f < 79.12 MHz. The REF_CLK will be a cleaner clock and may fix this sporadic issue. Additionally, is the DSI stream coming in with a clock of approx.185MHz? It looks like you're using the DSI_CLK-DIVIDER to divide the incoming clock speed by 3. 

  • 0 in reply to Vishesh Pithadiya
    Prodigy 30 points

    Thanks for the Feedback. Currently we don't have provision for REFCLK in our board and we will consider the implementation of a REF_CLK in the next revision. In the meantime, Can you suggest any solution that can be addressed through software? our DSI CLK currently measures approximately 200MHz. Please confirm that the configuration file shared is OK with respect to the Panel that we are using.

  • 0 in reply to Krithika T
    TI__Mastermind 23285 points

    Hey Krithika,

    The most important settings for sporadic issues like yours are register 0x0A, 0x0B, 0x10, and 0x12. 

    From your config:

    LVDS_CLK: 62.5MHz - 87.5 MHz

    DSI_CLK = 200MHz

    2 lanes used

    DSI_CLK_RANGE = 0x26

    A good test would be to try to increase DSI clock to approx. 187.5 MHz, so its not on the edge of the range intervals (5 MHz). This would mean that the DSI_CLK_RAGE you want to use would be 185 - 190 MHz. If you change this but keep your divider the same the output LVDS clcok should be 62.5 Mhz. This would able put you closer to the nominal DCLK of your panel which is 62.58 MHz, which may get rid of your sporadic issue. This will put you at the edge of the LVDS clock frequency range, but its closer to your ideal panel spec. 

    If this doesn't work simply try to find a combination of DSI_CLK, and LVDS_CLK that meets spec, and isn't an edge case for any of the range registers.

    Best,

    Vishesh Pithadiya

  • 0 in reply to Vishesh Pithadiya
    Prodigy 30 points

    Dear Vishesh,

    We are using 4 lanes. We will change the DSI_CLK_RANGE to 185-190MHz.

    Thanks and regards,

    Krithika T

  • 0 in reply to Krithika T
    TI__Mastermind 23285 points

    Let me know if you run into the same issues. If this doesn't fix the issue, the best route moving forward would be to implement a REF_CLK.