TUSB8041: TUSB8041IRGCR USB 3.0 and USB 2.0

Hi Venkatesa:

  Any update?

Regards

Brian

HI Brian,

Still We are facing same issue !

IF we are connecting Host mode the TUSB1210 Clock How will give external clock 26 MHZ or 60 MHz from processor ?

Hi Venkatesa:

   You can provide external 26Mhz clk to REFCLK pin, or you can provide 60Mhz clk to CLOCK  from ULPI interface.

   How do you provide clk right now?

Regards

Brian

We are giving external 26 mhz to ulpi ic and ULPI ic output clock 60 mhz giving to input to processor .for the host configuration this is fine?

Can you send tusb1210 schematic for  review?

Regards

Brian

HI Brian,

Below  image of the TUSB1210  schematic 

Currently, our hardware setup involves providing a 26 MHz REFCLK from an external clock generator for functionality. Additionally, the ULPI Clock outputs a 60 MHz clock, which is connected to the input clock of the FPGA processor.

But I have a doubt: in the device tree configuration, it's set to host mode only. In this case, does the host generate a clock of 60 MHz and provide it to the ULPI IC Input clock, right?

In default, CLOCK (pin 26) is input mode which get 60Mhz clock from FPGA ULPI. When REFCLK detect clock, CLOCK became output mode and send out 60Mhz clock. REFCLK input clock should be square clk over 3V.

  Did CPEN pin goes high?

  Resistor on ID can not be 0 ohm., but <1k ohm.

Regards

Brian

FPGA ULPI clock how configure in  processor side its input clock or output clock in xilinx vivado tool  ?

CPEN pin goes high yes 

Resistor ID resistor 1k configured 

Since you have 26Mhz clk on REFCLK of TUSB1210, , FPGA ULPI clock  in  processor side should be  configured as input clock .

Regards

Brian

Yes we are connected Input Ref clock in Processor ,

Can you Help me the ULPI driver wise what are things we need to take care

checked power sequence and Reset handled u boot level 

When connecting pen drive  "~# [   25.955399] usb usb1-port1: connect-debounce failed" this error coming 

Hi Venkatesa::

       What FPGA used for this design? You may contact FPGA vendor, they should have ULPI link code to start with.

       TI don't support driver/firmware development.

Regards

Brian

Hi Brian, 

I belong to the same team.

While debugging USB HUB, it was found that the register offset F0h of TUSB8041(USB HUB) was occupied with 0x00. As per the datasheet the 4th bit of this register is responsible for the output enable of USB Hub.Does this have any dependency on the present status of the USB HUB? Are we missing something at the configuration side of the USB HUB?

Hi Alex;

   default status for F0h is 0x00.  the 4th bit of this register is responsible for the output enable of USB connection status , not enable  or disable USB hub.

So no matter you change this bit or not, it will not affect any function of hub.

Regards

Brian

Thanks, Brian for the confirmation.

As per our Arhchitecture, Ports of the USB Hub are occupied with 5G modems which supports both USB 2.0 and USB 3.1 protocols. By default, which protocol will be selected. In my understanding, either of these two protocols can be selected at a time (is that correct?).

For any USB device, it will start with USB3 communication first, once USB3 is failed, it will downgrade to USB2 communication. .

Regards

Brian

Hi Brian,
Can you please confirm the Voh and Vol values for reset pin (GRST) in TUSB8041IRGCR ?

Hi Alex:

    GRST is input signal, why do you need Voh/Vol? Do you mean Vih/Vil? How is overall status.?

Regards

Brian

Sorry Brian, I mean the Vih/Vil only.

Still this issue is not resolved. We are working on this.

Hi Alex:

   Vil is 0.8v and Vih is 2v for GRST pin.

Regards

Brian

Hi Brian, 

When we have probed, it was observed that initially RESET is 3.3V at the time of RESET release and then it falls to stable 2V at the time of booting. The RESET doesn't have any external pullup and it is directly tied to SoC. Does it have any impact since the Vih is 2V.

GRST has internal pullup to 3.3v supply, can you check 3.3v supply during booting?

Regards

Brian

3.3V power supply side is still stable with permissible ripple ranges, Dip observed at reset side is attached here for your reference.

Are there any delay between 1.1v/3.3v and GRST signal?

Regards

Brian

There was no delay between 3.3V and GRST, we added a delay of 18.1ms by adding a 1uf capacitor between GRST and GND. But unfortunately, this also didn't work.

We have some latest updates regarding this issue. We tapped the DP, DN lines between the ULPI (TUSB1210) and USB HUB (TUSB8041) and a USB type A male connector was attached. Which was then connected to a PC, and we got the USB HUB (TUSB8041) getting detected. But we have noted that the current drawn by the 1.1V rail was much higher than that is mentioned in the datasheet: 

1. At the time working the current drawn between a range of 370mA-421mA, without any devices being connected to the TUSB8041 IC. The same current drawn even when the USB male connector was removed from the PC.

2.We tried to reset the IC by shorting the GRST pin with the gnd when the IC was working. But the current was at a range of 300mA (expected to be 28mA as per datasheet). And the IC was not responding after following this step (still the current drawn was 300mA). It again started responding only after a power cycle.

3.We also tried to reset the IC by shorting the GRST (with gnd) at the time of IC turn ON. Still the current drawn from 1.1V rail was at a range of 300mA.The IC didn't respond even after the reset release, and it started working only after power cycling.

What can be the reason for this?

Other than the above mentioned, can you please review the ULPI (TUSB 1210) reset scheme. Is there any recommendations to be followed?

Hi Alex:

    You mean USB2 hub can be detected if by-passing TUSB1210? Can USB3 hub detected?

   For TUSB1210, You need to remove the pullup on RESETB if you need to reset the upli bus.

   Can we have a call to sync the status?

Regards

Brian

Hi Brian,

Yes, we isolated TUSB8041 from ULPI chip and TUSB8041 is working fine independently. We were also able to transfer the data to a USB flash drive connected to the downstream of the TUSB8041 (mean while upstream was connected to a Laptop PC)  

Hi Brian, 

We have some more updates on ULPI transceiver as well (TUSB1210). We have removed the pull up resistor at the RESET signal and we added an additional circuit as shown below (Which was recommended by AMD, which gives a 1ms toggling pulse after reset release). As of now ULPI controller is found, and we are getting access to the ULPI registers. We are also able to control CPEN pin. We have connected a pen drive at the DP DN traces of ULPI IC too, after isolating TUSB8041, unfortunately this not getting detected and we are constantly getting an error called debounce failed. We also tried to take the dump of registers and we came to find that the ULPI transceiver is in Device Mode. What can be the reason for this?

This the additional circuit we added at the reset side using an AND Gate.

How is ID status? For host, ID should be grounded though 1k resistor.

Regards

Brian

Hi Brian,

We also tried by changing the ID resistor to 1K from 0E, but there is no change. Device is still in device mode.

Hi Alex:

   Was CPEN going high? CPEN was in CMOS mode?

   Another issue could be UTMI to ULPI interface ? Was it configured as host mode?

Regards

Brian

Hi Brian,

There was a miscommunication occurred between me and SW team. Actual scenario is ULPI phy controller inside the MPSoC is in Device mode and the ULPI IC is going to suspend mode(is this due to inactivity).

Is ID pin to be grounded with 1K is mandatory, in our schematics it is 0E(can u give reference for this in Datasheet)?

  Was CPEN going high? CPEN was in CMOS mode?  // Yes CPEN pin was going to high when gave "usb start" command was given in uboot and when we enter out of uboot(when it continues booting) it  cpens goes to low, then it comes back again almost at the end of booting(then it is stable high). And if we didn't stop at Uboot, CPEN turns stable high almost at the end of booting.

I have one more query, does this chip have any critical dependency on power sequencing. As per datasheet 3.3V should come before 1.8V.As per our design 1.8V and 3.3V comes in same power sequence(and 1.8V comes almost 4ms before 3.3V).I also tried by isolating and changing the sequence of TUSB1210 manually so that 3.3V(along with VBAT) will come first. But this also didn't show any changes.

there is a diode from VDDIO to VBAT which will be forward biased when VDDIO is present but VBAT is not present. Applying 1.8v before 3.3v to TUSB1210 is not recommended. also recommend isolate VDDIO and Vdd18.

For ID, here is reference in datasheet

Regards

brian

there is a diode from VDDIO to VBAT which will be forward biased when VDDIO is present but VBAT is not present. Applying 1.8v before 3.3v to TUSB1210 is not recommended. also recommend isolate VDDIO and Vdd18. /// Does this have any role on the present status of Board

4ms is pretty long If 1.8V comes almost 4ms before 3.3V, It may cause power on reset fail. At least 1.8V and 3.3V comes in same power sequence.

Regards

Brian