DS90UB960-Q1: DS90UB960-Q1: Suggested PCB Stackup

Hello Connor,

This really depends on the complexity of your design. As long as you can route all high-speed signals over a continuous GND reference plane, all high-speed signals are spaced away from all neighboring signals and power rails (S>3W), and proper length-matching is achievable, then a 6 layer PCB is possible.

Your 6-layer PCB sounds okay, but I am not sure of your design requirements or if you can fit everything in 6 layers. The PCB stackup just needs to be symmetrical, which means that each layer above/below the core would need to have the same height. However, this does not strictly define the functionality of each layer. You don't have to strictly only route Power on 1 layer and GND planes on the layer above/below it. But if there are a lot of high-speed signals or the dimensions of your PCB are restricted, then you may have to add layers to allow for more isolation and prevent crosstalk/coupling.

The 8-Layer stack-up seems a bit redundant, with multiple GND layers on top of each other. One example of an 8-Layer stack-up is:

SIG - GND - SIG - GND/PWR - GND/PWR - SIG - GND - SIG

L1 -> L8

High-speed signals routed on L1, L3, L6, and L8 must be routed over a continuous GND plane. Power planes are also routed on L4 and L5, but they are not routed on top of each other. No high-speed signals are routed over a PWR plane.

For anti-pads:

If you route a high-speed signal, then it must always be routed over a continuous GND plane. The trace must also be strictly impedance controlled (e.g. 50-Ohms (+/-10%) single-ended or 100-Ohms (+/-10%) differential). Impedance of a trace consists of multiple factors, such as trace width, distance from the trace to the surrounding GND copper pour, the height of the PCB layer, dielectric material used, etc... If you are on the Top Layer and have a component landing pad touching the high-speed trace, then the landing pad will increase the width of the PCB trace and introduce impedance mismatch. To minimize impedance mismatch, we recommend increasing the distance between the PCB trace and its GND reference plane, to push the impedance of the trace back within the 50 or 100 Ohms tolerance.

If normally, the high-speed trace is on L1 and you have a GND reference plane on L2, then at the landing pad, you can cut-out the GND plane on L2 just around the landing pads of the capacitors touching the high-speed trace. This will leave an empty space on L2, so the trace on L1 can reference the GND plane on L3 or below.

If the touching landing pad is relatively small (0402 or 0201), then adding an anti-pad through 1 layer is normally enough. But if the touching landing pad is much larger (0603 or more), then there is typically sharper impedance mismatch and cutting multiple layers may be required. Impedance really depends on the specific stack-up. You can use a calculator tool, such as Saturn, or you can reach out to your fab house to get a recommendation on achieving impedance control. But running a simulation on the trace or using a TDR on the built board is better for confirmation.

Best,

Justin Phan

Hello Connor,

It seems you are using an RG-178 flexible coaxial cable and an SMB connector in your design. If this is a test board, then that's fine. But typically, customers use automotive grade connectors for improved mechanical strength and reduce EMI/EMC.

For this specific type of surface-mount SMB connector, I believe the default footprint listed in the datasheet is fine. The only issue I would see is if excess solder is added to the data pin.

For impedance, if your PCB layer thickness is optimized such that the width of the PCB trace is the same width as the data pin landing pad of the SMB connector while achieving 50-Ohms impedance, then you don't need to add an anti-pad. If the SMB connector SMB landing pad is thicker than the PCB trace coming into it, then you may have to evaluate if it is necessary to add an anti-pad, using a calculator tool like Saturn. Depending on the calculation, you can choose to add or not add an anti-pad depending on which option better maintains 50-Ohms impedance through the connector.

For the Channel Requirements, the Total Channel Requirements are defined here:

There is no specific requirement for the IL/RL across the PCB traces or cable. As long as you meet the Total Channel Requirements across two PCBs and a cable (under high temperature and current load conditions), then our SER/DES devices will work as intended.

The PCB stackup is only a means to meet our Layout Guidelines. As long as you have a stack-up that allows you to route the high-speed FPD-Link traces over a continuous GND plane, maintain 50-Ohms (+/-10%) single-ended impedance all the way from the SER device to the DES device, don't route any noisy signals near the high-speed signal (S>3W), and try to keep the PCB traces as short as possible (to minimize Insertion Loss), choose a cable with decent loss characteristics, choose a dielectric material with decent loss characteristics, then you have the best chance of meeting our Total Channel Requirements.

If you can't route your high-speed traces to follow these guidelines with your current stack-up, then you may need to add more layers or increase the dimensions of your board.

IL/RL on the high-speed line also heavily depends on the layout. After performing layout, the only way to get more confirmation on the IL/RL characteristics is to either run a simulation with a software tool like ANSYS, or take physical measurements.

Best,
Justin Phan