DS90UB924-Q1: VDDIO and VDD33 back drive phenomenon

Hey Kailyn,

Can you send me a scope shot of all VDDs and PDB showing the ramp time for each Vdd rail and the capture waveform with respect to each other as follows. 

We need to check the rise time and delay compare to datasheet recommendation. 

Regards,
Fadi A.

Hi Fadi A，

Thank you very much for your reply. The power up sequence is as following: 

Best regards

Kailyn

Hey Kailyn,

Can you please zoom into the VDD waveofrms and measure the rise time. Please see power sequence diagram above - I need measurements of t0/t1/t3 and t4. 

Regards,
Fadi A.

Hi Fadi A,

Thank you for your reply.

Please refer to the curve about VDDIO and VDD33. The right curve is also the timing which remove the step.

Best regards

kailyn

Hi Kailyn, 

Thank you for the update. I will take a look on this issue while Fadi is out on business travel. 

Best,

Shu

Hi Kailyn, 

Can you share the customer schematic too? Also is this just happening on a single system or are there multiple boards seeing the same backdrive VDD33 waveform at power up? 

Best,

Shu

Hi Shu,

Thank you very much for your reply, below is the schematic, and according to the customer's feedback, he tested two boards and they both have the same phenomenon:

Best regards

kailyn

Hi Kailyn, 

From the schematic, the power supplies show a lot more power decoupling caps than our datasheet recommended application diagram. This maybe causing the VDD33 to show the step-like charging when powered up closely after VDDIO. The 100nF caps are more sensitive to noise and should be placed closer to the pin on the PCB, if not already. Can the customer rework the VDD33 rail to have a 4.7uF coupling cap like the datasheet suggests?

Best,

Shu