DS250DF230: Reset Time

Hi Nishe-san,

(Q1) What is the minimum time READ_EN_N must be asserted low before it can be de-asserted high in order for reset to take effect?

(A1) I would recommend pulling READ_EN_N low for at least 15 us for reset to take effect.  Please note that after reset is released, there is some additional reset time.  For this reset time, I would refer to the power on reset assertion time spec in the datasheet, which is a maximum of 50 ms.

(Q2) How long does it take to reset with Address 0x0A? According to the Programming Guide, the CDR Reset is expected to be complete after one access time of the SM Bus. Is this correct? 

(A2) Yes, CDR reset will take effect immediately after the register write.  Please keep in mind that CDR reset is functionally different than a complete device reset.  Also after releasing CDR reset, the retimer will need to re-acquire CDR lock.  Please reference the data sheet for CDR lock times.

(Q3) I understand that the HW reset in (1) initializes register settings and all circuits in the device, and the SW reset in (2) initializes only circuits related to CDRs. Where in the internal block diagram are the circuits that are not initialized by the SW reset but are initialized by the HW reset?

(A3) It is challenging to give a clear divide between which functional blocks are and are not impacted by CDR reset without defining some additional criteria.  I would look at CDR reset as a state machine reset, while the hardware reset involves state machine resets and register configuration resets.

Looking at the device block diagram, the CDR reset has no impact on the register configuration of any of the function blocks.  For example, the CDR reset will not change which adapt mode the receiver is using, and will not impact TX FIR settings.

However, the CDR reset has a direct impact on the state of many functional blocks in the retimer.  CDR reset will cause the CDR functional block to re-acquire CDR lock.  As the retimer re-acquires CDR lock, it will re-adapt the RX settings.  This means that CDR reset has an impact on CTLE and DFE functional blocks.  Additionally, the retimer output will be muted until CDR lock is acquired, so the TX driver will not be in use until CDR lock is acquired.

Additionally, I notice you only referenced CDR reset.  Please keep in mind that there are also register resets that may be useful.  Please see channel register 0x00[2] and shared register 0x04[6].

Thanks,

Drew