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SN65LVDS31: Rise-time on enable pin

Lyto
Prodigy 120 points
Part Number: SN65LVDS31

Dear TI-support-team,

what is the necessary rise-time on the enable pin (G) for the SN65LVDS31. We have G/ tied to Vcc and on G, we use a RC-circuit that is tied to Vcc to delay the enable of the LVDS-driver for about 20ms.

Is this okay and allowed?

Thank you

  • 0
    TI__Genius 15321 points

    Hi Lyto,

    Figure 8-4 shows the timing diagram and the relationship between the enable pin and output signals. If you look at the functional block diagram in section 9.2, the device functional modes (Table 9-1), and Figure 8-4, you can see that there is no need to add a RC circuit to delay the enable pin.

    You can also refer to the schematic for the EVM here: Low Voltage Differential Signaling (LVDS) EVM User's Guide

    Regards, Amy

  • 0 in reply to Amy
    Prodigy 120 points

    Hello Amy,

    thank you for your response. I know the timing diagram and I know there is no need for a delay, but we want to implement a delay for our application. That´s why we built in a RC-circuit in front of the enable bin. But the question is: is the slow RC rise-time on the enable pin allowed. How does the internal enable circuit look like; does it allow such a slow transition?

    Thank you

  • +1 in reply to Lyto
    TI__Genius 15321 points

    Hi Lyto,

    Figure 8-4 mentions that all input pulses were tested with tr or tf in less than 1ns. However, in Table 9-1 with the truth table with the input and enables, it appears that a slow rise time on an enable would be allowed. The case to watch for is the enable pin being L and H at the same time, as this can cause an indeterminate output. To mitigate this, ensure that at any given point in time one of the enables is in a guaranteed high or low state.  

    Let me know if you have other questions.

    Regards, Amy