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DS160PT801X16EVM: Lane count in case of 2x4 bifuraction

Part Number: DS160PT801X16EVM
Other Parts Discussed in Thread: DS160PT801

Hi,

I am going to use DS160PT801 re-timer for 2x4 bifurcation mode. Please let me know what will the combination for Lane0?

A_PET0 and A_PETR0- for TX

B_PET0 and B_PETR0 for RX

will create one lane(LANE0)

Please confirm, my understanding is correct or not?

Other Queries are-

1. If i am not using EEPROM then can we programmed it via SoC over I2C?

2. Since i am using it for backplane application which works on separate clock architecture, then what will be the termination require on lock
REFCLK+/- pins since it is input reference clock.

3. A Port and B port are interchangeable - means either port can be connect to SoC or back-plane?

Thanks

Sagar

  • Hi Sagar,

    The lane numbers of the retimer are assigned during PCIe link training by the protocol. An example 2x4 configuration would be:

    • x4 link #1: Channels A0-A3, B0-B3
    • x4 link #2: Channels A4-A7, B4-B7

    Please take a look at the PRT

    1. Yes, the retimer can be programmed over SMBus while system PERST# is held low. Note that pull-up resistors are still required on EEPROM SMBus lines even if not used.
    2. I am not sure I completely understand this question. Could you please specify what you mean when you state "termination requirement on lock"?
    3. Yes, this understanding is correct.

    Please note that, if you have additional questions related to the full data sheet or secure documents, please contact either your TI FAE for further assistance, or we can discuss over private E2E message.

    Best,
    David

  • Hi David,

    Q2. I am not using refclk because we are having a separate clock architecture then can we leave floating input side of refclk+ (Y5) and refclk- (V5) ?

    Thanks

    Sagar

  • Hi Sagar,

    The DS160PT801 requires REFCLK input at pins Y5 and V5. These input pins cannot be terminated in a valid configuration.

    The DS160PT801 may use a separate PCIe reference clock if desired - the supported REFCLK architectures are outlined in data sheet section 9.3.8.

    If you have further questions about the supported REFCLK architectures, please send me a message on private E2E message.

    Best,
    David

  • Hi David,

    I have this datasheet SNLS550A – DECEMBER 2020 – REVISED JULY 2022 where it does not have and 9.3.8 section regarding refclk separate clock architecture.

    My other Query is-

    1. If I am not using EEPROM and SMBUS(Selected SoC is not supporting SMBUS), can we do initial flash over I2C lines?? since in datasheet they mentioned- I2C configuration (up to 1 MHz) through the external EEPROM or I2C controller. Please confirm

    Thanks

    Sagar

  • Hi Sagar,

    I apologize for the confusion, I had meant to state Section 8.3.8.

    If programming using I2C, the I2C controller must adhere to the SMBus timing requirements outlined in Section 7.7 of the data sheet of DS160PT801. Is there a specific parameter you are concerned about?

    Best,
    David

  • Hi David,

    Thanks for your reply.

     So i need to connect I2C lines of SoC to SMBUS line of retimer not I2C Lines of Retimer. Please confirm.

    I have few more queries-

    1. If I am using 1x8 single chip configuration then what will the connection on following pins?- PRT0_RST#, PRT1_RST# and MODE pins

    2. Please let me I/O standard level of refclk I/P pins (HCSL, CML, LVPECL)? I just want to know whether we need to add AC coupling caps on REFCLK Input pins or not?

    Thanks

    Sagar

  • Hi Sagar,

    Please accept my friend request for E2E private message so that we can discuss these questions further, as this information is not publicly available.

    Best,
    David

  • Hi David,

    I dropped private message to you.

    Thanks

    Sagar

  • Hi Sagar,

    I've followed-up offline on your posed questions.

    Best,
    David