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DP83867IR: Compatibility and configuration query

Rishav Verma
Prodigy 20 points
Part Number: DP83867IR

Hi, 

We need to use DP83867IRRGZR in our project, please confirm the phy is compatible with the TI processor AM3352BZCZ, 

Also, answer my below queries regarding the design of the same,

1. We are Using VDDIO= 3.3 and other voltage rails as 1.0, 1.8 and 2.5 as per the specs defined, what is the timing requirements of the voltage rails, if it is not feasible to supply all the rails at once, what is the tolerance on the delay, it is given for 1.8v and 2.5v please suggest for other voltage rails, or is it ok if we power in any sequence for all the rails.

2. What is preferred for the clock source as per TI, crystal 25 mhz or oscillator powered with 1.8V 25mhz,

3. Suggest if in the system where RMII was configured with 50Mhz clock, the clock 25Mhz suitable with RGMII is there any other preference which leads to less system level changes, what are the system level changes in this case, also share the linux support package for the same. 

4. Is there series termination resistors required on the driver side of the clock and data bits between the phy and processor.

5. Is TG1G-E012NZLF suitable for the operation, also suggest if we should short the center terminal of the magnetics currently populated with 0E jumper and 0.1uf caps.

6.Is there any pullup requirement on the differential line, or it is internally available

Thanks,

Rishav 

  • 0
    TI__Genius 17826 points

    Hi Rishav,

    Yes the DP83867 is compatible with the AM3352BZCZ. For future reference, for a processor and PHY to be compatible, check to see if they support the same MAC interfaces. The AM3352BZCZ supports GMII & RGMII, which the DP83867IR also supports.

    Please find my responses below.

    1. We are Using VDDIO= 3.3 and other voltage rails as 1.0, 1.8 and 2.5 as per the specs defined, what is the timing requirements of the voltage rails, if it is not feasible to supply all the rails at once, what is the tolerance on the delay, it is given for 1.8v and 2.5v please suggest for other voltage rails, or is it ok if we power in any sequence for all the rails.

    • The only requirement is that VDDA1p8 come up within 25 ms or at the same time of VDDA2p5

    2. What is preferred for the clock source as per TI, crystal 25 mhz or oscillator powered with 1.8V 25mhz,

    • Either Crystal or Oscillator is okay, as long as the meet the specs mentioned in Sections 9.2.1.2 & 9.2.1.3 of the data sheet.

    3. Suggest if in the system where RMII was configured with 50Mhz clock, the clock 25Mhz suitable with RGMII is there any other preference which leads to less system level changes, what are the system level changes in this case, also share the linux support package for the same. 

    • The linux support will be the same
    • The DP83867IR does not support RMII. 

    4. Is there series termination resistors required on the driver side of the clock and data bits between the phy and processor.

    • No series termination resistors are required between PHY and processor

    5. Is TG1G-E012NZLF suitable for the operation, also suggest if we should short the center terminal of the magnetics currently populated with 0E jumper and 0.1uf caps.

    • Please compare Transformer Specs with requirements listed in Table 9-1 Magnetic Isolation Requirements in the data sheet.

    6.Is there any pullup requirement on the differential line, or it is internally available

    • Please see section Section 9.2.1.1 of the data sheet for all MDI side connections.

    Regards,

    Alvaro