SN65DP159: N Channel output not functioning

Hey Richard,

Im looking into this now, I'll get back to you as soon as I can.

Can you confirm that the input signals are differential not single ended? Also please send the I2C configuration you are using for this device.

Hi Vishesh,

I am the designer on this project.  Yes the input signals are differential.  We are currently using an Intel/Altera reference design as the HDMI source we diagnose this issue.  I have scoped the inputs and they look fine.  The N output legs are essentially stuck at 0.  

My design uses a reference design … exactly like two demo designs I’ve reviewed in the past.  My fpga has timing closure, I can probe the diffential signals entering the retiming chip and they look fine.  VCC,VDD, GND all good. 

 Additional Info:

The P side of the diff outputs seem to be fine 300mV or so signal, atop, 3.0V DC.  For some reason the N side of the output are not functioning properly (on all 4 diff pairs).  The N side sits at about 0V with 150mV of signal which looks to be in phase with its P counterpart. 

Also, chip is in I2C mode and using default settings.  The 159 appears to be snooping the EDID data properly and setting the bitrate, etc.  I have tried lots of different settings in regs 0x09,0x0A,0x0B... without success.  

thank you for your attention to this.  

mike (mike@chipcraft.com)

Mike

When you are probing the output pins, are you probing directly at the DP159 output pins or somewhere else?

Thanks

David

On the inputs: directly on the DP159 (DP159 side of the ac coupling caps). 

On the outputs: probing DP159 side of the DLW21SN900HQ2L and on a HDMI breakout board. 

thanks,

Mike

I've been racking my brain on this... Another thought I had was perhaps latch-up.  However, the spec indicates there are no real power sequencing requirements... and the DP159 does not get "latch-up hot".   

Mike

On the DP159 OE pin, do you have a 0.22uF pull down capacitor? 

On the output clock lane, can you replace the DLW21SN900HQ2L with 0 ohm resistors and see if there is anything on the negative channel?

Thanks

David

I do not have the pull down capacitor.  I drive the OE pin from the fpga.  I initialize OE low.  I then hold OE low for 200us following the fpga plls being locked. I then assert OE.  

Mike

On the output clock lane, can you replace the DLW21SN900HQ2L with 0 ohm resistors and see if there is anything on the negative channel? If you still see the issue, are you seeing this issue on multiple boards?

Thanks

David

we are thinking alike... Was contemplating shunting the common mode chokes.  I was also contemplating tacking in the pull-down cap and tri-stating the oe trace... those are the only two things that are different from the spec ref design.    

all boards are affected.

Mike

I agree with your approach. If you can tri-state the FPGA I/O pin that drives the OE pin and have a pulldown capacitor on it, this will create a passive reset circuit and we can see if it resolves this issue. 

If you are still seeing an issue with 0-ohm resistor instead the choke, then I would also double check the DP159 thermal pad solder connection. The schematic does show the thermal pad is connected to the board ground, and the datasheet requires to have at least 75% solder coverage on the thermal pad.

Does this issue happen across multiple resolution?

Thanks

David

Yes it is independent of resolution.  I'll first try the passive reset circuit.  

thanks again,

Mike

Hey Mike,

Kindly keep us updated with your findings. Additionally double check the terminations of the output lanes as well. 

Will do.  With any luck I'll have some feedback today.  

Passive reset circuit had no effect.  Reworking board to remove chokes and shunt the choke pads.