DP83848C: RMII design

Mike Singer

Part Number: DP83848C
Other Parts Discussed in Thread: DP83848J,

Are TI engineers available to review a schematic design? I am working with DP83848C (RMII mode) interfacing to a PIC32MX795F512L device. What lines should be impedance controlled, just the clock and data lines? I have been referencing a prior design (with DP83848J). Based on the strapping I see it appears to be RMII mode as well, but several lines not required for RMII are also routed and connected. I would like someone to have a look and verify I have what I need for RMII if possible.

6 months ago

0 Gerome Cacho 6 months ago

TI__Mastermind 31755 points

Hi Mike,

For schematic and layout designs, TI Ethernet has crafted a checklist for customers to utilize to expedite schematic reviews due to their familiarity with the design. However, if any questions were to arise from the initial checklist, we can happily assist further. I have also provided the layout checklist as a just-in-case attachment.

To answer your question, all single ended traces should be 50 Ohm impedance controlled while all differential (in this case MDI) should be 100 Ohm differential impedance controlled.

1033.DP83848_Schematic_Design_Review_Checklist.xlsx IndustrialPHY_Layout_Review Checklist_New.xlsx

Sincerely,

Gerome

Interface

Interface forum

DP83848C: RMII design