Other Parts Discussed in Thread: DP83TD510E
Hi all,
Is it possible to use EtherCAT with your SPE PHYs?
We are using the Sitara AM64 with the industrial communication EtherCAT stack from TI and would like to use them with either 10Base-T1L or 100Base-T1 PHYs if possible. For this we consider using the DP83TC81-2/3/4 or DP83DT510E. Certification is not necessarily important, because we will use it for internal communication first.
The application note on SPE for industrial robotics mentions EtherCAT, but the PHYs are using RGMII there (EtherCAT on AM64 uses MII) and we could not draw a clear conclusion from that. (https://www.ti.com/lit/an/snla420a/snla420a.pdf?ts=1709896782580&ref_url=https%253A%252F%252Fwww.google.com%252F)
Now there are some sources regarding the PHY requirements:
and
which I have taken from this thread: - https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1308347/am6442-custom-boards-without-the-dp83869-phy-chip-can-have-other-ways-or-patches-to-adapt-to-the-am64x-industrial-communications-sdk-ethercat_slave_simple_demo_am64x-evm_r5fss0-0_freertos_ti-arm-clang-routines-in-09-00-00/4996318#4996318
The main requirements listed (with my own remarks after the -----):
1. The PHYs have to comply with IEEE 802.3 100BaseTX or 100BaseFX ----- Requirement not fulfilled by the PHYs which are 100Base-T1, but if using e.g. the DP83TC812 exclusively in the whole system that may not be a problem?
2. The PHYs have to support 100 Mbit/s Full Duplex links. ----- Fulfilled by the DP83TC812, but not the DP83TD510E which is only 10MBits. Same as above though, if only DP83TD510E will be used throughout the system including the Master, should work anyways?
3. The PHYs have to provide an MII (or RMII/RGMII1) interface. ----- Fulfilled by both.
4. The PHYs have to use autonegotiation in 100BaseTX mode. ----- Fulfilled by DP83TD510E except it being 10Base, but not by DP83TC812, does this even matter though? Because using these standards, they only work with that one speed anyways?
5. The PHYs have to support the MII management interface. ----- Fulfilled by both.
6. The PHYs have to support MDI/MDI-X auto-crossover in 100BaseTX mode. ----- That usually applies to two twisted pairs, here we are having only one, so just ignore this?
7. The PHYs must not modify the preamble length. ----- Doesn't seem like they do, so fulfilled I suppose.
8. The PHYs must not use IEEE802.3az Energy Efficient Ethernet. ----- No mention of it in the Datasheets.
9. Receive and transmit delays should comply with the standard (RX delay should be below ~320 ns, TX delay below ~140 ns), ----- RX delays is below 300 for both, couldn't find anything for TX.
10. Minimum cable length is 0 m ----- What would be less than that? Ignore this I suppose.
11. The PHYs must offer the RX_ER signal (MII/RMII) or RX_ER as part of the RX_CTL signal (RGMII). ----- Fulfilled by both.
12. PHY link loss reaction time (link loss to link signal/LED output change) should be faster than 15 µs to enable redundancy operation2 ---- No mention of it in the DP83TC812. The DP83TD510E datasheet on the other hand says "The DP83TD510E includes advanced link-down capabilities that support various real-time applications." which is also below 15us, and the mentioning of real-time systems gives me a bit of confidence that we could use EtherCAT with it.
Our goal is to get the EtherCAT protocol provided by TI on the AM64/AM24/AM26 working with the SPE PHYs (10 or 100Base, the 1000Base does not have MII). Any hint on why this would not be possible and render this scenario ultimately not feasible is greatly appreciated. Apparently the PHYs don't meet the specs but I suppose they were written without SPE in mind.
Cheers,
Ergin
