DP83867IS: CLK_OUT: Receive clock if there is no link?

Alexander Stein

Part Number: DP83867IS

Hi,

I'm currently configuring my ethernet PHY to output the receive clock divided by 5, resulting in 25 MHz on a 1Gbit/s link.

Using a logic analyzer I could verify the write sequence as follow:

Reg_0x0D=0x001F
Reg_0x0E=0x0170
Reg_0x0D=0x401F
Reg_0x0E=0x40F

This actually results in a clock output pf 25 MHz.

But I am wondering why I do still get a 25 MHz clock if there is no link and the PHY is configured as link slave (Register 0x9 set to 0x1300).
I would have expected to see no clock output if there is no receive clock. Could someone clarify how can I verify I get the ethernet switch clock.

Thanks and best regards,
Alexander

10 months ago

0 Hillman Lin 10 months ago

TI__Mastermind 25025 points

Hi Alexander,

May I ask which pin are you measuring? Are you measuring the CLK_OUT pin? If so, could you try the following and see if CLK_OUT is disable:

Reg_0x0D=0x001F
Reg_0x0E=0x0170
Reg_0x0D=0x401F
Reg_0x0E=0x044F

Regards,

Hillman Lin

0 Alexander Stein 10 months ago in reply to Hillman Lin

Prodigy 10 points

Hello,

yes I am measuring at CLK_OUT pin. I can diable CLK_OUT as you described. This results in a permanent low level, as expected.

Setting register 0x170 to 0xF (channel A receive clock) also results in a 125MHz output. Everything is without a link.

Thanks and best regards,
Alexander

0 Hillman Lin 10 months ago in reply to Alexander Stein

TI__Mastermind 25025 points

Hi Alexander,

Glad that it work on your side.

Regards,

Hillman Lin

0 Alexander Stein 10 months ago in reply to Hillman Lin

Prodigy 10 points

Hi,

there seems to be a misunderstanding.

Configuring the CLK_OUT mode was never the issue, see my first post. Instead the output was configured as "receive clock divided by 5". But there was no link, so my assumption is there is no receive clock to forward. Contrary to my expectations I could still see a 25 MHz clock, even though there is no link, see the question's topic.

How can I configure statically the PHY so I have the following behavior:

no link: no clock on CLK_OUT
with link: receivce clock / 5 => 25 MHz on 1GBit/s link

Please advise. Thanks and best regards
Alexander

0 Hillman Lin 10 months ago in reply to Alexander Stein

TI__Mastermind 25025 points

Hi Alexander,

Please correct me if my understanding is wrong.

Right now, you are still seeing 25MHz on 1Gbps even if you have no link and configure the register 0x0017 to 40F?

Regards,

Hillman Lin

0 Alexander Stein 10 months ago in reply to Hillman Lin

Prodigy 10 points

Hi,

exactly. I would expect there is no clock out if there is no link.

Thanks and best regards,
Alexander

+1 Hillman Lin 10 months ago in reply to Alexander Stein

TI__Mastermind 25025 points

Hi Alexander,

We check it in the lab, it seems like the received clock only show up when the link is up. Without link, the clock signal is still 25MHz.

The first figure is without link and second figure is with link. You can see that the clock is sync when the link is on that indicate CLK_OUT is configure receive clock successfully when the link is up.

Regards,

Hillman Lin

0 Alexander Stein 10 months ago in reply to Hillman Lin

Prodigy 10 points

Hi,

thanks for the eleborate analysis. Just for a confirmation and to be clear: To put it in other words, there is always a clock on CLK_OUT. If there is a link it's synchronized to the receive clock. Without link the clock is derived from PHY internals?

Did I get this right?

Thanks and best regards,
Alexander

0 Hillman Lin 10 months ago in reply to Alexander Stein

TI__Mastermind 25025 points

Hi Alexander,

Yes, Alexander your understanding is correct.

Regards,

Hillman Lin

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DP83867IS: CLK_OUT: Receive clock if there is no link?