SN75DP159: PLL is not lock，The picture of the display is abnormal

Simon Chan said:

Through the debugging tool (EyeScanTool) to connect the IIC of the target board chip DP159, it is found that DP159 has a high probability of PLL not lock problem when the system is powered on for the first time (as shown in Figure 1).At this time, the display is visually normal

Is the display abnormal or normal? the title says one thing and the text says another. Additionally what resolution are you trying to display.

At this time,the display is normal, The resolution we try to display is 3840*2160@60HZ.The title says abnormal condition occasionally occurs during the display process.

Hi Vishesh Pithadiya

    Thanks for your rfeply.

   I use Automatic retimer for HDMI2.0 now，not the Automatic redriver to retimer crossover at 1.0 Gbps (default),and we've always used 4k60 resolution，so there will be no data rate change and no mode conversion.

Hey Simon,

Are you able to send the DDC log when you see the PLL drop?

HI Vishesh Pithadiya

   The log from SOC is in  Figure 1.

Figure 1

The data captured from the DDC(using a logic analyzer) in real time is shown in Figure 2.

Figure 2

Would it be possible for you to send the DDC data in the following format. Its very difficult to decode DDC data in the format you have sent,

159 ddc.xlsx

Hi Vishesh Pithadiya

    PLease check The Excel .

    In addition,please make sure that the PLL unlock will lead to the flash screen or black screen.And how does the SOC get the out-of-lock event  when PLL is not lock.

Hi Vishesh Pithadiya

  Thank you for your reply.I have two question.

  Question1: Will the PLL unlock lead to the flash screen?

  Question2:how does the SOC get the out-of-lock event  when PLL is not lock?

Hi Vishesh Pithadiya

   We only use HDMI2.0.,so there is not from HDMI1.4 to HDMI2.0 situation.

The EDID shows that TMDS clock ratio is 1/10 as register 0x20 is 0x01. When you go to write 0x03 looks like the connection is lost. This means that when the system tries to get up to a TMDS clock ration of 1/40 the connection is broken. This is why there is a pll unlock. 

what is the resolution you are using? is it close to a data rate of 3.4 Gbps?

Additionally are you following this procedure before transitioning the clock ratio?

Hi Vishesh Pithadiya

    I don't think this is what caused the PLL to lose lock,becouse it is not every time a unlock of PLL occurs,and it can revert to lock when I pull  and plug HDMI wire.One more point,our motherboard design references Xilinx's evaluation board,but  it don' t occur  a unlock of PLL in the Xilinx's evaluation board when we use the same display.

  Please answer an important question, Vishesh Pithadiya.how does the SOC get the out-of-lock event  when PLL is not lock?Which register needs to be read to get the PLL's state,the datasheet makes no mention of it.

  Thank you very much!

Hey Simon,

Does your customer have an NDA with TI? I cannot share which register monitors the PLL status because it is confidential.

A workaround that my be helpful is monitoring register 0x20, and whenever there is a change from value 03 in that register you most likely have a PLL drop. In this case you will want to restart the device in your driver.

HI Vishesh

   Thank you for your reply.

   Your workaround may be helpful to the PLL drop question,.And based on your experience,do you think there is a great correlation between PLL drop and flash screen?

HI Vishesh

   We are  not an agent now but a direct user. How do we need to sign the NDA with TI?

Yes, typically when the PLL drops this means that the retimer connection between the input an output is lost. This means that the redriver is simply using equalization and there is no jitter clean-up functionality. If you don't see any signal quality issue when the PLL drops I recommend looking into a redriver vs. a retimer for your solution to save costs.

Please reach out to the TI local office and they will assist you in the process. I unfortunately cannot help with that.

Hi Vishesh

  I don't see any signal quality issue when the PLL drops now,so I want the SOC to monitor register of PLL status in real time to check whether the PLL drop when the screen flashes.And I'm not sure I understand your advice.

Hi Vishesh

   Look at the picture below，the PLL drops,  but the device does not configure into redriver mode.Why?

Hmm that is weird, this may be an input clock jitter issue. Please have a look at this e2e thread and try to expand your PLL bandwidth, this may fix your issue.

link: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1111325/sn65dp159-sn65dp159?tisearch=e2e-sitesearch&keymatch=SN65DP159

Hi  Vishesh

     This method can fix my issue.To better verify it, I still want to know how to get PLL status,please.

     Also, I have a question, can you explain the meaning of "the Page 1 registers" in the image below?

     Is it possible having a private mail exchange?

    Thanks!