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TLK10081: Device Configuration for SGMII

Markus Becker
Prodigy 40 points
Part Number: TLK10081

Good Day,

i want to transmit and receive SGMII (1,25Gbps) Signals, via the TLK10081 Device.

LS Input --> 8 Lanes SGMII -- HS Output --> 10Gbps SFP+

The Lane Order would be important.

Can you give me please a recommendation how i should configure the TLK's register for this application?

Thank you, for your support!

Best Regards

Markus

  • 0
    TI__Mastermind 21955 points

    Hi Markus,

    Unfortunately we don't have any formal bringup procedures available for TLK10081. Here are some key registers which may need to be configured for this application. I recommend you still review the entire register map.

    • Setting HS/LS data rates: Refer to section 5.1 of the datasheet. Configure with registers 0x02, 0x03, 0x06, 0x07.
    • 8 lane mode: Enable with 0x01[3:2] (default setting).
    • Lane ordering: Refer to section 3.3 of the datasheet. Configure with registers 0x16, 0x17, 0x18.
    • Link training: Enable/disable with 0x01[14].
    • Interleaving mode: Select word interleave or bit interleave with 0x01[9:8].
    • HS/LS EQ settings: Configure with registers 0x04, 0x08. Some tuning may be required.

    To clarify, you wish to use TLK10081 to aggregate 8 lanes of SGMII (1.25 Gbps) into 1 lane of 10 Gbps going to an SFP+ module? Note that this device does not support 10 GbE, which is 64b/66b encoded and has a line rate of 10.3125 Gbps.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 40 points

    Hi Lucas,

    yes, in my case 8 Lanes (1,25Gbps) into 10Gbps, 8b/10b. Is there a document, beside the datasheet, which describes the registers in more details? Most registers are self explanatory, but some registers are not.


    Macro Access??
    Primary Macro??
    HS_SERDES_CONTROL_3??
    Difference between LS_TX__Lane_DELAY and SKEW_CONFIG_CONTROL??
    Divided Rate Control??
    GIGE MODE??
    ADC Track Mode??
    Lane Oversampling??

    Best Regards

    Markus

  • +1 in reply to Markus Becker
    TI__Mastermind 21955 points

    Hi Markus,

    Unfortunately we don't have another document which describes register values in detail. Here is some additional explanation for the register settings listed.

    • Macro Access: Used to select a HS port for register reads and writes.

    • Primary Macro: Primary macro refers to channel A HS port and alternate macro refers to channel B HS port.
    • HS_SERDES_CONTROL_3: This register controls various EQ settings on the HS receiver. Descriptions are given for each setting in the datasheet register map.
    • SKEW_CONFIG_CONTROL: This register controls which LS lanes should be included in skew alignment.

    Transmit direction:

    Receive direction:

    • LS_TX_LANE_DELAY: Writing 0x0A[3]=1'b1 overrides TX skew config settings and enables skew control through LS_TX_LANE_DELAY. LS_TX_LANE_DELAY can be used to manually add skew to the lane selected in LS_LN_CFG_EN.
    • Divided Rate Control: LN_RX_DIV_RATE and LN_TX_DIV_RATE bits are used when individual LS lanes have different rates. This setting is not applicable in a 8 x 1.25 Gbps to 10 Gbps application.
    • GIGE Mode: This is a setting which assists in 1 GbE applications.
    • ADC Track Mode: This is a HS EQ setting which typically improves signal quality in short channel applications. Some testing may be required to determine if ADC track mode should be used in your application.
    • Lane Oversampling: LS_RX_OVERSAMPLING and LS_TX_OVERSAMPLING are used when a LS lane is configured to a higher rate than the signal's actual data rate, meaning the device "oversamples" the signal. This setting is not applicable in a 8 x 1.25 Gbps to 10 Gbps application.

    Best,

    Lucas