DS90UB941AS-Q1: Why did 941 register reset ?

yang yanliang

Prodigy 150 points

Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: ALP, USB2ANY

Hello TI team,

Why did 941 register reset itself?

We encounter occasional flickering/black screen phenomenon, and the software detects that the 924_LOCK is link down;

Verify Item:

1.941 1.1V ,1.8V ,PDB are stable, and No I2C Write when 941 register reset;

2.941 patten mode also flicker/black;

HW plateform: QC8155+941+924,DSI as a clock source,Port 1 connect to CID, Port 0 floating

What: screen flicker/black;

Why: 941 register Reset-->941_PIN20 power off--->FPDLINK disconnect（Port1）------>924_LOCK link down---->screen flicker/black

Who： CID display

When: Product normal running, random;

Where: Vehicle

over 1 year ago

0 Jack Scherlag over 1 year ago

TI__Mastermind 38245 points

Hi Yan,

yang yanliang said:
Why did 941 register reset itself?

It's not clear to me that there was a reset of the 941. From the screenshot I just see register reads and writes over I2C. Can you clarify what you mean?

yang yanliang said:
We encounter occasional flickering/black screen phenomenon, and the software detects that the 924_LOCK is link down;

Does the flickering/black screen happen at the same time after system startup? Does it always occur on every power cycle?

In the diagram, I see that there is a crystal connected to the 941AS, but it is running in single-link mode. You also mentioned that the DSI clock is used as the clock source. A possible cause of this flicker could be the 941AS switching clock references.

Could you see if the flickering stops if PCLK_AUTO is disabled? I cannot guarantee this will work since I do not know enough about your configuration.

Best,

Jack

0 yang yanliang over 1 year ago in reply to Jack Scherlag

Prodigy 150 points

Hello Jack,

Thanks for you reply quickly, and sorry for misunderstand, let me explain more info...

1. The hardware configuration mode_sel0 is 7 through the resistor（10K/OPEN）, but in fact, the working mode needs to be selected 3, so the software configuration 0X5B is 0x00（auto-detect）; But after 924 LINK, we read 0X5B and found that its value changed to 0X07(reset value,forced splitter mode);

---->So we judge the occurrence of 941 register reset

---> and We tried configuring mode_sel0 to mode 3 via hardware resistors（13K/10K）, but it still flickered;

2. Occurs after working for a period of time, without regularity, not at start-up,no power off/on;

3.externel crystal is reserved components.

Hope to hear from you again, thanks.

0 yang yanliang over 1 year ago in reply to Jack Scherlag

Prodigy 150 points

For Auto-detect/ single-link,Can just use PORT1? PORT0 Hardware Reserved; Are there any risks?

0 Jack Scherlag over 1 year ago in reply to yang yanliang

TI__Mastermind 38245 points

Hi Yan,

yang yanliang said:
For Auto-detect/ single-link,Can just use PORT1? PORT0 Hardware Reserved; Are there any risks?

Auto-detect can function with Port 1 only. There is no forced single FPD3 mode for Port 1 only so Auto-detect is the only option for this configuration. By default, the device is biased towards Port 0 operation so the TX_PORT_SEL register needs to be set to write/read from Port 1 registers.

yang yanliang said:
---> and We tried configuring mode_sel0 to mode 3 via hardware resistors（13K/10K）, but it still flickered;

2. Occurs after working for a period of time, without regularity, not at start-up,no power off/on;

Based off of this, the MODE_SEL configuration and mode of operation isn't causing the flicker. My guess is that this could be a marginal link issue due to the fact that it occurs without regularity and after a period of time.

Can you provide the following information

941AS register dump before flicker and after flicker
Type and length of cable used

One way to test if link marginality is causing loss of lock is to use the MAP (Margin Analysis Program) tool. This requires a direct connection to the deserializer and ALP.

MAP App note: Link

Best,

Jack

0 yang yanliang over 1 year ago in reply to Jack Scherlag

Prodigy 150 points

Hi Jack,

thanks for you reply agian;

1.There are 941AS register attached;

2.LVDS cable lenth is 50CM;

3.We tested Link margin (941+cable+924) from I2C of 924 with USB2ANY;

===============================================

Our main point is why the 941 register reset ;

4.even if the FPDLINK signal is not good, it will not cause the 941 reset, right?

Sync Latest progress, it is found that 941_PDB signal will have some ns time noise from the vehicle GND. 941_PDB is directly controlled by SOC through GPIO.
5.Will such a short time of noise cause 941 reset?
6.What is the debounce time of PDB signal? The datsheet mentions that must held low minimum 2ms;

================================================

Fullscreen TI941 after flicker log.txt Download

Register Display - ALP Nano 1 - DS90UB941AS, Connector 1

Register	Data	Name
0x0000	0x1A	I2C_DEVICE_ID
0x0001	0x00	RESET_CTL
0x0002	0x00	DEVICE_CFG
0x0003	0x92	GENERAL_CFG
0x0004	0x00	GENERAL_CFG2
0x0005	0x00	I2C_MASTER_CFG
0x0006	0x58	DES_ID / 
DES_ID_1
0x0007	0x00	SlaveID[0]
0x0008	0x00	SlaveAlias[0]
0x0009	0x01	SDA_SETUP
0x000A	0x10	CRC_ERROR0
0x000B	0x00	CRC_ERROR1
0x000C	0x67	GENERAL_STS
0x000D	0x30	GPIO[0] Config
0x000E	0x00	GPIO[1] and GPIO[2] Config
0x000F	0x00	GPIO[3] Config
0x0010	0x00	GPIO[5] and GPIO[6] Config
0x0011	0x00	GPIO[7] and GPIO[8] Config
0x0012	0x00	DATAPATH_CTL
0x0013	0x8F	TX_MODE_STS
0x0014	0x00	TX_BIST_CTL
0x0016	0xFE	BCC_WDOG_CTL
0x0017	0x1E	I2C_CONTROL
0x0018	0x7F	SCL_HIGH_TIME
0x0019	0x7F	SCL_LOW_TIME
0x001A	0x01	DATAPATH_CTL2
0x001B	0x00	BIST_BC_ERRORS
0x001C	0x0C	GPI_PIN_STS1
0x001D	0x00	GPI_PIN_STS2
0x001E	0x01	TX_PORT_SEL
0x001F	0xFA	FREQ_COUNTER
0x0020	0x03	DES_CAP1
0x0021	0x00	DES_CAP2
0x0026	0x00	LINK_DET_CTL
0x002E	0xA5	MAILBOX_2E
0x002F	0x5A	MAILBOX_2F
0x0030	0x00	REM_INTB_CTRL
0x0032	0x00	IMG_LINE_SIZE0
0x0033	0x05	IMG_LINE_SIZE1
0x0034	0x0C	IMG_DELAY0_IMG_DELAY0_P1
0x0035	0x00	IMG_DELAY1_IMG_DELAY_P1
0x0036	0x00	CROP_START_X0 / 
CROP_START_X0_P1
0x0037	0x00	CROP_START_X1 / 
CROP_START_X1_P1
0x0038	0x00	CROP_STOP_X0 / 
CROP_STOP_X0_P1
0x0039	0x00	CROP_STOP_X1 / 
CROP_STOP_X1_P1
0x003A	0x00	CROP_START_Y0 / 
CROP_START_Y0_P1
0x003B	0x00	CROP_START_Y1 / 
CROP_START_Y1_P1
0x003C	0x00	CROP_STOP_Y0 / 
CROP_STOP_Y0_P1
0x003D	0x00	CROP_STOP_Y1 / 
CROP_STOP_Y1_P1
0x003E	0x81	SPLIT_CLK_CTL0 / 
SPLIT_CLK_CTL0_P1
0x003F	0x02	SPLIT_CLK_CTL1 / 
SPLIT_CLK_CTL1_P1
0x0040	0x10	IND_ACC_CTL
0x0041	0x94	IND_ACC_ADDR
0x0042	0x00	IND_ACC_DATA
0x004F	0x8C	BRIDGE_CTL
0x0050	0x16	BRIDGE_STS
0x0054	0x02	BRIDGE_CFG
0x0055	0x10	AUDIO_CFG
0x0056	0x00	BRIDGE_CFG2
0x0057	0x02	TDM_CONFIG
0x0058	0x00	VIDEO_3D_STS
0x0059	0x00	DUAL_DSI_CTL_STS
0x005A	0xE9	DUAL_STS / 
DUAL_STS_P1
0x005B	0x07	DUAL_CTL1
0x005C	0x07	DUAL_CTL2
0x005D	0x06	FREQ_LOW
0x005E	0x44	FREQ_HIGH
0x005F	0x21	DSI_FREQ / 
DSI_FREQ_P1
0x0060	0x22	SPI_TIMING1
0x0061	0x02	SPI_TIMING2
0x0062	0x00	SPI_CONFIG
0x0063	0x00	VCID_SPLIT_CTL
0x0064	0x10	PGCTL / 
PGCTL_P1
0x0065	0x00	PGCFG / 
PGCFG_P1
0x0066	0x00	PGIA / 
PGIA_P1
0x0067	0x00	PGID / 
PGID_P1
0x006A	0x00	IMG_HSYNC_CTL0 / 
IMG_HSYNC_CTL0_P1
0x006B	0x00	IMG_HSYNC_CTL1 / 
IMG_HSYNC_CTL1_P1
0x006C	0x00	IMG_HSYNC_CTL2 / 
IMG_HSYNC_CTL2_P1
0x006D	0x00	BCC_STATUS
0x006E	0x20	BCC_CONFIG
0x006F	0x00	FC_BCC_TEST
0x0070	0x00	SlaveID[1]
0x0071	0x00	SlaveID[2]
0x0072	0x00	SlaveID[3]
0x0073	0x00	SlaveID[4]
0x0074	0x00	SlaveID[5]
0x0075	0x00	SlaveID[6]
0x0076	0x00	SlaveID[7]
0x0077	0x00	SlaveAlias[1]
0x0078	0x00	SlaveAlias[2]
0x0079	0x00	SlaveAlias[3]
0x007A	0x00	SlaveAlias[4]
0x007B	0x00	SlaveAlias[5]
0x007C	0x00	SlaveAlias[6]
0x007D	0x00	SlaveAlias[7]
0x00C2	0x00	CFG
0x00C4	0x00	STS
0x00C6	0x00	ICR
0x00C7	0x00	ISR
0x00F0	0x5F	TX_ID0
0x00F1	0x55	TX_ID1
0x00F2	0x42	TX_ID2
0x00F3	0x39	TX_ID3
0x00F4	0x34	TX_ID4
0x00F5	0x31	TX_ID5

Fullscreen TI941 before flicker log.txt Download

Register Display - ALP Nano 1 - DS90UB941AS, Connector 1

Register	Data	Name
0x0000	0x18	I2C_DEVICE_ID
0x0001	0x00	RESET_CTL
0x0002	0x00	DEVICE_CFG
0x0003	0x82	GENERAL_CFG
0x0004	0x00	GENERAL_CFG2
0x0005	0x00	I2C_MASTER_CFG
0x0006	0x00	DES_ID / 
DES_ID_1
0x0007	0x00	SlaveID[0]
0x0008	0x00	SlaveAlias[0]
0x0009	0x01	SDA_SETUP
0x000A	0x00	CRC_ERROR0
0x000B	0x00	CRC_ERROR1
0x000C	0x64	GENERAL_STS
0x000D	0x30	GPIO[0] Config
0x000E	0x05	GPIO[1] and GPIO[2] Config
0x000F	0x03	GPIO[3] Config
0x0010	0x00	GPIO[5] and GPIO[6] Config
0x0011	0x00	GPIO[7] and GPIO[8] Config
0x0012	0x00	DATAPATH_CTL
0x0013	0x8F	TX_MODE_STS
0x0014	0x00	TX_BIST_CTL
0x0016	0xFE	BCC_WDOG_CTL
0x0017	0x1E	I2C_CONTROL
0x0018	0x7F	SCL_HIGH_TIME
0x0019	0x7F	SCL_LOW_TIME
0x001A	0x01	DATAPATH_CTL2
0x001B	0x00	BIST_BC_ERRORS
0x001C	0x00	GPI_PIN_STS1
0x001D	0x00	GPI_PIN_STS2
0x001E	0x04	TX_PORT_SEL
0x001F	0x00	FREQ_COUNTER
0x0020	0x00	DES_CAP1
0x0021	0x00	DES_CAP2
0x0026	0x00	LINK_DET_CTL
0x002E	0xA5	MAILBOX_2E
0x002F	0x5A	MAILBOX_2F
0x0030	0x01	REM_INTB_CTRL
0x0032	0x00	IMG_LINE_SIZE0
0x0033	0x05	IMG_LINE_SIZE1
0x0034	0x0C	IMG_DELAY0_IMG_DELAY0_P1
0x0035	0x00	IMG_DELAY1_IMG_DELAY_P1
0x0036	0x00	CROP_START_X0 / 
CROP_START_X0_P1
0x0037	0x00	CROP_START_X1 / 
CROP_START_X1_P1
0x0038	0x00	CROP_STOP_X0 / 
CROP_STOP_X0_P1
0x0039	0x00	CROP_STOP_X1 / 
CROP_STOP_X1_P1
0x003A	0x00	CROP_START_Y0 / 
CROP_START_Y0_P1
0x003B	0x00	CROP_START_Y1 / 
CROP_START_Y1_P1
0x003C	0x00	CROP_STOP_Y0 / 
CROP_STOP_Y0_P1
0x003D	0x00	CROP_STOP_Y1 / 
CROP_STOP_Y1_P1
0x003E	0x81	SPLIT_CLK_CTL0 / 
SPLIT_CLK_CTL0_P1
0x003F	0x02	SPLIT_CLK_CTL1 / 
SPLIT_CLK_CTL1_P1
0x0040	0x10	IND_ACC_CTL
0x0041	0x94	IND_ACC_ADDR
0x0042	0x00	IND_ACC_DATA
0x004F	0x8C	BRIDGE_CTL
0x0050	0x16	BRIDGE_STS
0x0054	0x02	BRIDGE_CFG
0x0055	0x10	AUDIO_CFG
0x0056	0x00	BRIDGE_CFG2
0x0057	0x02	TDM_CONFIG
0x0058	0x00	VIDEO_3D_STS
0x0059	0x00	DUAL_DSI_CTL_STS
0x005A	0xE9	DUAL_STS / 
DUAL_STS_P1
0x005B	0x00	DUAL_CTL1
0x005C	0x07	DUAL_CTL2
0x005D	0x06	FREQ_LOW
0x005E	0x44	FREQ_HIGH
0x005F	0x44	DSI_FREQ / 
DSI_FREQ_P1
0x0060	0x22	SPI_TIMING1
0x0061	0x02	SPI_TIMING2
0x0062	0x00	SPI_CONFIG
0x0063	0x00	VCID_SPLIT_CTL
0x0064	0x10	PGCTL / 
PGCTL_P1
0x0065	0x00	PGCFG / 
PGCFG_P1
0x0066	0x00	PGIA / 
PGIA_P1
0x0067	0x00	PGID / 
PGID_P1
0x006A	0x00	IMG_HSYNC_CTL0 / 
IMG_HSYNC_CTL0_P1
0x006B	0x00	IMG_HSYNC_CTL1 / 
IMG_HSYNC_CTL1_P1
0x006C	0x61	IMG_HSYNC_CTL2 / 
IMG_HSYNC_CTL2_P1
0x006D	0x00	BCC_STATUS
0x006E	0x20	BCC_CONFIG
0x006F	0x00	FC_BCC_TEST
0x0070	0x00	SlaveID[1]
0x0071	0x00	SlaveID[2]
0x0072	0x00	SlaveID[3]
0x0073	0x00	SlaveID[4]
0x0074	0x00	SlaveID[5]
0x0075	0x00	SlaveID[6]
0x0076	0x00	SlaveID[7]
0x0077	0x00	SlaveAlias[1]
0x0078	0x00	SlaveAlias[2]
0x0079	0x00	SlaveAlias[3]
0x007A	0x00	SlaveAlias[4]
0x007B	0x00	SlaveAlias[5]
0x007C	0x00	SlaveAlias[6]
0x007D	0x00	SlaveAlias[7]
0x00C2	0x80	CFG
0x00C4	0x40	STS
0x00C6	0x21	ICR
0x00C7	0x04	ISR
0x00F0	0x5F	TX_ID0
0x00F1	0x55	TX_ID1
0x00F2	0x42	TX_ID2
0x00F3	0x39	TX_ID3
0x00F4	0x34	TX_ID4
0x00F5	0x31	TX_ID5

0 Jack Scherlag over 1 year ago in reply to yang yanliang

TI__Mastermind 38245 points

Hi Yan,

Thank you for attaching registers and MAP results.

yang yanliang said:
4.even if the FPDLINK signal is not good, it will not cause the 941 reset, right?

Yes, the 941 does not reset itself. Only the PDB pin, power cycle, or I2C commands will reset the device.

yang yanliang said:
5.Will such a short time of noise cause 941 reset?
6.What is the debounce time of PDB signal? The datsheet mentions that must held low minimum 2ms;

The noise present on the PDB pin is causing a violation of the absolute max ratings which will lead to unpredictable behavior from the device. The minimum allowed voltage on PDB is -0.3v and from the graph I can see voltages exceeding -4.5v.

This noise needs to be decoupled from the PDB pin. Has the source of the noise been determined? Can decoupling caps be attached to the net to reduce the noise?

Best,

Jack

0 yang yanliang over 1 year ago in reply to Jack Scherlag

Prodigy 150 points

Hi Jack

Thank you again for your reply.

The source of the noise has not been determined yet, because the vehicle GND system is very complicated.
1. We find that it is an effective way to improve the current ability of SOC to drive 941_PDB from 2mA-> 16mA. Can 941_PDB withstand the current capacity of 16mA? Are there any other risks?
2.PDB signal from the layout point of view of the inner layer should not be disturbed, then it is likely that the 941 internal GND has been interfered, is this correct analysis?

3. What I want to ask is that although the waveform of PDB exceeds that of spec, will only the time of ns affect the chip?

0 Jack Scherlag over 1 year ago in reply to yang yanliang

TI__Mastermind 38245 points

Hi Yan,

yang yanliang said:
1. We find that it is an effective way to improve the current ability of SOC to drive 941_PDB from 2mA-> 16mA. Can 941_PDB withstand the current capacity of 16mA? Are there any other risks?

The PDB pin max input high current is 100µA and the max input low current is 20µA.

yang yanliang said:
2.PDB signal from the layout point of view of the inner layer should not be disturbed, then it is likely that the 941 internal GND has been interfered, is this correct analysis?

I don't have enough information on the hardware to make an input on this.

yang yanliang said:
3. What I want to ask is that although the waveform of PDB exceeds that of spec, will only the time of ns affect the chip?

This is an unknown. If we wanted to determine if this noise is the cause of the device reset, we would to see if there is a correlation between 924 lock loss and the PDB noise. These could be both traced on an oscilloscope simultaneously.

There are some other questions I have

Are there other systems with this same issue?
Does the MCU/SoC issue any other commands after initialization?
- Is it possible the reset is software issued?
In the "before flicker" register dump, there is no link to the 924. Was this intentional?

Best,

Jack

0 yang yanliang over 1 year ago in reply to Jack Scherlag

Prodigy 150 points

Hi Jack,

1.Although the maximum value of 941_PDB is 100uA, but SOC is the output 16mA, will it damage 941 PDB PIN? Where's the excess current?

2..Yes,We judge that 941_PDB Noise--- > 941 Reset-- > 924 lock loss is correlation ，The noise seems to only affect 941_PDB

3. Other systems no this issue, both MCU and SOC are normal, Because the another screen（cluster） is normal, and the music sound is normal.

0 yang yanliang over 1 year ago in reply to Jack Scherlag

Prodigy 150 points

Does the 941 have register to improve the anti-interference ability?

+1 Jack Scherlag over 1 year ago in reply to yang yanliang

TI__Mastermind 38245 points

Hi Yan,

yang yanliang said:
1.Although the maximum value of 941_PDB is 100uA, but SOC is the output 16mA, will it damage 941 PDB PIN? Where's the excess current?

Was the SoC output current measured? Or is this just the max current the SoC pin can drive?

A current above the listed max in the data sheet can potentially damage the device.

yang yanliang said:
Does the 941 have register to improve the anti-interference ability?

There is no register than can correct for this interference. It is the responsibility of the hardware to ensure the data sheet specifications are met.

yang yanliang said:
The noise seems to only affect 941_PDB

Are the power supplies not affected?

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DS90UB941AS-Q1: Why did 941 register reset ?