DS160PR810EVM-RSC: Regarding the reference board DS160PR810EVM-RSC, I have some question

Hi Jason,

jason hu said:

1. In the reference design, only the data signals of PCIe have been redriven, while the clk signals of PCIe have not undergone redrive. Is the attenuation of the refclk comparatively lower than that of the data signals, such that it can be used normally even if not processed as in the reference design? Additionally, can the refclk be enhanced with a redrive card like the data signals are?

The redriver is not intended to drive clock signals. The 100 MHz PCIe clock is much lower in frequency than the PCIe signals and does not experience meaningful attenuation in any system I have worked with, so I would not see any need to alter the clock signal even if the end application was a large server board for example. To my knowledge, there are no redriver products intended for clock signals and using a PCIe/Ethernet/etc. redriver would not work because the frequency regions they work on are not suitable for clock signals.

jason hu said:

2. Can a single DS160PR810 handle two port X4 width PCIe links simultaneously, thereby utilizing all 8 LANs effectively?

All 8 channels on the DS160PR810 are pointing in one direction, so technically a single DS160PR810 device cannot support any link by itself because links require two directions of communication. However if you mean that your application idea would have 1x DS160PR810 in the downstream direction and 1x DS160PR810 in the upstream direction, then such a system could be bifurcated into two x4 links without problems.

Currently, TI's only bidirectional redriver is the 16-lane DS320PR1601 or the similar Gen 4 version DS160PR1601 (16 channels in each direction, total 32 channels on one chip), which is quite big. If your application idea is to have 4 downstream channels and 4 upstream channels in the same chip, the only alternative I know is to to use two distinct DS160PR410 or DS320PR410 4-channel redrivers, one handling each direction. This may take slightly more board space than a single DS160PR810 size chip but the performance may be better due to the smaller package, and many of our customers who are working with x4 SSDs use the 4-channel redrivers this way.

jason hu said:

3.In the reference design, why is the ground resistance of J14 different from what is described in Table 2-1?

On the EVM schematic I see that J14 (GAIN_DS, gain settings for downstream devices) has the following ground straps:

Table 2-1 of the datasheet says this:

The reason for the difference is that the EVM connects all four GAIN pins belonging to the two downstream DS160PR810 devices to a single jumper J14. Each four-level control pin on the device such as GAIN has an internal voltage comparator that can approximately "read" what strap resistance is applied to them. The EVM wants to control four GAIN pins at the same time using the same settings and has them connected to the same node, so the resistor straps can be simplified using parallel logic:

So you can notice how 1k / 4 ≈ 249 Ohms, 13k / 4 ≈ 3.24k Ohms, 59k / 4 ≈ 14.7k Ohms.

This method is used by TI Gen4/Gen5 PCIe redriver EVMs to save board space and simplify operation of the EVM, it may or may not be relevant to a full-size customer design but is good to know.

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Feel free to continue on this thread if you have other questions about the DS160PR810 or the EVM reference design. If you are working on a project with the DS160PR810 or other TI devices in the future, you can forward any questions or schematics to your TI FAE contact and we will be happy to assist or review.

Best,

Evan Su