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TLK10081: ethernet link aggregation

Ece dbs
Prodigy 10 points
Part Number: TLK10081
Other Parts Discussed in Thread: DP83869HM, DP83869, TLK10022, TLK10034, TLK10232, TLK10031

Hi, I'm working on an application that aggregates 2 gigabit ethernet into a single high-speed link bidirectionally like this:

(LS) 2 x RJ45 (1000/100/10BASE-T) MDI <---> PHY <---> 2 x 1.25 Gbps (SGMII) <---> 10 Gbps HS Link (Fiber/Copper/wireless) <---> 2 x 1.25 Gbps (SGMII) <--> PHY <---> 2 x RJ45 (1000/100/10BASE-T) (LS)  

My questions are:

1) Is it a suitable diagram if i do not use any media converters like for copper to fiber? I don't care about the protocol transferred in High-speed transmission channel.

2) If I use a PHY device SGMII with Reference Clock (625 mhz) ( to support Synchronous Ethernet, is it suitable for synchronous clocking of the Low Speed Side of the TLK10081 like diagram BELOW?

Or, I'm thinking about using multiple port PHY device which has more than one SGMII outputs. If synchronization is satisfied by the internal clocking of PHY, is it suitable for TLK10081?

3) Can I use 8 LS input from directly 4 twisted pair of Gbit Ethernet x 2 (from 2 x RJ45) and use bit interleave mode for raw data (1000Mbps / 4 = 250 Mbps per pair)? Actually, I don't care about the data rate here, It can be 100base-t or something else, wondering if I can use raw ethernet data as input of TLK10081 or something else.

Hope that my questions are clear, thank you for your support,

Ece

  • 0
    TI__Mastermind 19730 points

    Hi Ece,

    Ece dbs said:
    1) Is it a suitable diagram if i do not use any media converters like for copper to fiber? I don't care about the protocol transferred in High-speed transmission channel.

    I'm assuming this is referencing connecting the 10 Gbps HS link to the TLK10081? TLK supports copper directly. Fiber is supported with the use of an SFP module. TLK does not support wireless.

    Ece dbs said:

    2) If I use a PHY device SGMII with Reference Clock (625 mhz) ( to support Synchronous Ethernet, is it suitable for synchronous clocking of the Low Speed Side of the TLK10081 like diagram BELOW?

    Or, I'm thinking about using multiple port PHY device which has more than one SGMII outputs. If synchronization is satisfied by the internal clocking of PHY, is it suitable for TLK10081?

    TLK10081 does not support 625 MHz reference clock. If you are able to divide this clock in half, a 312.5 MHz reference clock is sufficient for 1.25 Gbps on the LS side and 10 Gbps on the HS side. Please refer to section 5 "Clocking" of the datasheet for more information.

    I'm assuming your application will include 2 x TLK10081 on either side of the HS link. Data on the LS and HS sides of the device will be synchronous with the refclk. But I don't see a way for both TLK devices to remain synchronous on the same clock domain, unless the 312.5 MHz refclk is sent over the HS link and connected to both TLK devices. Therefore I don't believe Synchronous Ethernet can be supported in this application.

    Ece dbs said:
    3) Can I use 8 LS input from directly 4 twisted pair of Gbit Ethernet x 2 (from 2 x RJ45) and use bit interleave mode for raw data (1000Mbps / 4 = 250 Mbps per pair)? Actually, I don't care about the data rate here, It can be 100base-t or something else, wondering if I can use raw ethernet data as input of TLK10081 or something else.

    TLK10081 does not support 1000BASE-T or raw ethernet data. 1 GbE data needs to be 1000BASE-X (8b/10b encoded).

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 10 points

    Hi,

    Thank you for your response,

    About the 2nd question, I was planning to use 1 x Multiport PHY and 1 x TLK10081 for both sides assuming that they can work in bidirectional. So, with a single Multiport PHY device, Low Speed Side ethernet SGMII signals will be in phase with the same clock, actually that was what i meant by synchronization.

    And about the 3rd one, can you confirm that if I use a media converter like DP83869HM to transfer 1000BASE-T data to 1000BASE-X, i can implement bit interleave mode for each pair (250mbps) right?

    Also, I wonder if there are any other ASICs implementing different data rate ranges for data aggregation. Maybe lower speed rate at HS link side?

    Thanks a lot for your help.

  • 0 in reply to Ece dbs
    TI__Mastermind 19730 points

    Hi Ece,

    Ece dbs said:
    About the 2nd question, I was planning to use 1 x Multiport PHY and 1 x TLK10081 for both sides assuming that they can work in bidirectional. So, with a single Multiport PHY device, Low Speed Side ethernet SGMII signals will be in phase with the same clock, actually that was what i meant by synchronization.

    Can you clarify, are you planning to have a system which looks similar to this block diagram with 1 x TLK10081 and 1 x Multiport PHY?

    In this application, the LS input to HS output signal path will be in phase with the 312.5 MHz reference clock since the PHY will synchronize the data signals and clock signal. The HS input to LS output signal path won't necessarily be in phase with the reference clock.

    Ece dbs said:
    And about the 3rd one, can you confirm that if I use a media converter like DP83869HM to transfer 1000BASE-T data to 1000BASE-X, i can implement bit interleave mode for each pair (250mbps) right?

    Yes, DP83869 can be used to convert between 1000BASE-T and 1000BASE-X. Note that I am not an expert on this device. If you have any technical questions related to DP83869, I suggest you open a new E2E thread and it will be assigned to the corresponding team.

    On the TLK10081, bit interleave mode can be used on the LS input signals. Can you clarify, what is the rate 250 Mbps in reference to? 1000BASE-X specifies an 8b/10b encoded single differential pair at 1.25 Gbps.

    Are you considering using DP83869 as the multiport PHY in this application? Or will the DP83869 be placed before/after the PHY?

    Ece dbs said:
    Also, I wonder if there are any other ASICs implementing different data rate ranges for data aggregation. Maybe lower speed rate at HS link side?

    TLK10022 supports up to 4 LS links (0.25 to 2.5 Gbps) aggregated to 1 HS link (1 to 10 Gbps). Unlike the TLK10081, The HS rate can be configured to operate at 1x, 2x, 3x, or 4x the LS rate. For your application with 2 x 1.25 Gbps links, the HS side can operate at 2.5 Gbps.

    TLK10232, TLK10031, and TLK10034 are XAUI/10G-KR transceivers which also support a general purpose SERDES mode. This mode can be used similarly to TLK10022.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 10 points

    Hello, 

    Thank you for suggestions. I was talking about 2 possible design that looks like above diagram. What I want is synchronization of multiple LS input signals (Let's say signal1A and signal2A are in different phase at rj45 side, on board A) so that after they transmitted in HS link and decoded on LS side on the other board, i can receive the signal1B in the same phase with signal1A and signal2B same with Signal2A respectively.

    So signals are synchronized by phy, can i use an external refclk for tlk10022 rather than using phy clock output in this application?

  • +1 in reply to Ece dbs
    TI__Mastermind 19730 points

    Hi Ece,

    Thank you for clarifying your proposed system design.

    Yes, you can use an external refclk with TLK10022 and TLK10081 instead of a PHY clock output. In the receive direction of the TLK (HS input to LS output), I expect the LS outputs will be in phase with each other.

    Best,

    Lucas