DP83867IR: Packet loss

Hi Malakondareddy,

The internal schematic for the jack looks good. Can you confirm if the jack meets our recommended specs listed in Table 9-1 Magnetic Isolation Requirements of our data sheet?

DP83867IR/CR Data sheet

The https://www.ti.com/product/DP83867IR#design-tools-simulation product page also has a Design Review Checklist. Please use this to go over your design. 

Regards,

Alvaro

Hi Alvaro (Al-vuh-roe) Reyes,

Thanks for the reply

Please find the isolation and other details in below attached images.

Is it okay to connect 3.3 VCC and GND connection to all center tapped capacitors? Since in your EVM design it mentioned that separate centre tapped capacitors second merged and connected to GND.

Thanks Alvaro,

I have tried with VCC (2) pin  left floating but Unfortunately the speed came down to 100Mbps instead 1000Mbps. However it is working perfectly after shorting pin 1 and pin 2 and connected through 0.01uF capacitor to ground. 

Could you please share if you have any document related what Magjack (Ethernett) connector for particular Ethernet phy controller  (voltage/current mode) ?

Also Please let us why it was not working 1000Mbps when 2 pin left floating and why it is giving packet loss when connect 3.3V to VCC pin ? 

Thanks & Regards,

B Malakondareddy

Hi Malakondareddy,

Leaving Pin 2 floating should work for 1000Mbps. Could you compare your schematic with this design: 

https://www.ti.com/tool/TMDS64EVM#design-files

Schematic can be found in the sprr462b.zip\PROC101D Design Files\Schematics folder.

It also uses the DP83867 with a LPJG16314A4NL mag jack.

Regards,

Alvaro

Hi Alvaro,

I gone through link (www.ti.com/.../TMDS64EVM and found that DNL for FB26 (it means floating 2nd pin). Did you really DNL that part in final PCB?

Also you mentioned that you have used LPJG16314A4NL in your testing. Did you used as-is or floated the 2nd pin ?

Regards,

B Malakondareddy.

Hi Malakondareddy,

Yes the FB26 is NOT included in the final board design, meaning pin 2 of the LPJG16314A4NL Magjack is left floating.

Regards,

Alvaro

Thanks for valuable information,

From all these conversations I understand that for voltage mode PHY controller we have to use voltage mode magjack/ normal jack with voltage mode magIC. Similarly for current mode PHY controller we have to use current mode magjack/ normal jack with current current mode magIC.

Please correct if I am wrong and also please share if you any material which is related this information. Or Please share any waveforms which we have faced same ethernet pack loss problems since I couldn't capture the waveform due to oscilloscope range (we have a basic oscilloscope).

Finally let we know if you any TI tools to simulate this.

With best regards,

 Malakondareddy 

Hi Malakondareddy,

Were you able to find any differences in the schematic? On the https://www.ti.com/product/DP83867IR#design-tools-simulation page we have a design review checklist. If you fill it out and return to me, along with your schematic, I can review it.

Just to confirm, the board does not work at all when you disconnect VCC? Unable to get link, ping, or transmit any data?

Regards,

Alvaro

Sorry to late reply. I could not reply due to some personal problem.

There is no difference between my schematic and yours.

when I disconnect VCC pin that time I saw data transmitting at 100Mbps instead of 1000Mbps. I am not sure why this is happening.

However If short VCC pin and GND and connected to PCB ground through 0.01uf this time it was working 1000Mbps without any packet loss. 

Could you know why it worked when short VCC and GND ? Image attached  for your reference.

Hi Malakondareddy,

Was hoping that you resolved this issue!

Apologies for not replying today, I did not have time to review your query today, please allow me another day to respond.

Regards,

Alvaro

Hi Malakondareddy,

This is very interesting, by shorting pins 1 & 2 you are bypassing the 0.1uF capacitor in the mag jack and then connecting a 0.01uF capacitor to PCB ground. This 100% solved the issue?

With VCC(2) left floating, the 867 links up at 100 Mbps? Do you have register access to the PHY, if so could you give a register dump of Registers 0x0 - 0x1F of both cases (VCC floating and VCC shorted to ground with the cap)?

Regards,

Alvaro

Hi Alvaro,

Yes it is working perfectly when I short VCC and gnd and connect to PCB GND through 0.01uf.

sudo ethtool eth0 showed 100Mbps when I left float the VCC(2). I could not access the register using sudo ethtool -d eth0 

Hi Malakondareddy,

If this configuration works for you, please continue using it.

You can also use phytool  to read registers:

phytool read eth0/(PHY ADDRESS)/(Desired Register to Read)

Regards,

Alvaro