DP83867E: DP83867E generates 125MHz RX_CLK at 100Mbps

Amy Liu

Part Number: DP83867E

Hello,

We were testing the MII loopback mode. We noticed that the PHY chip generated 125MHz RX_CLK when the link was established at 100Mbps. We expected 25MHz RX_CLK.

Here are the register settings to enable MII loopback after the link had established at 100Mbps.

0x0010: clear bit 6 to disable auto-mdix

0x0000: 0x4140

0x00FE: 0xE720

0x001F: set bit 14 to soft reset

Any ideas?

Thanks,

Amy

9 months ago

+1 Gerome Cacho 9 months ago

TI__Mastermind 34475 points

Hi Amy,

For 100Mbps manual communication, shouldn't Reg 0x0 = 0x6100 instead of 0x4140? The manual speed selection in that case is 1000Mbps, which falls into line with 125MHz on RX_CLK.

Sincerely,

Gerome

0 Amy Liu 9 months ago in reply to Gerome Cacho

Prodigy 30 points

Hi Gerome,

Good catch! We were able to get MII loopback working after forcing the chip to 100Mbsp and full duplex during initialization after a reset.

Thanks so much for your help!

Amy

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DP83867E: DP83867E generates 125MHz RX_CLK at 100Mbps