• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 32 subscribers
  • Views 220 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867E: Can't force 1000Mbps full duplex

Amy Liu
Prodigy 30 points
Part Number: DP83867E

Hello,

The PHY chip was able to establish 1000Mbps full duplex if auto-negotiation was enabled. However, if we disabled auto-negotiation and forced 1000Mbps full duplex, the chip was unable to establish the link for some reason. Did we miss anything here?

Register settings:

0x0000: 0x0140

Thanks,

Amy

  • +1
    TI__Mastermind 34475 points

    Hello,

    According to IEEE802.3, this configuration is not supported. If 1G communication is required, it will need to go through auto-negotiation.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 30 points

    Hi Gerome,

    Good to know! When we enabled MII loopback at 1000Mbps, the EMAC driver didn't get any Rx interrupts after sending out a packet. Do you know what could be the problem? Both RX_CLK and TX_CLK are 125MHz.

    Thanks so much!

    Amy

  • 0 in reply to Amy Liu
    TI__Mastermind 34475 points

    Hi Amy,

    I don't understand the concern. You are saying Rx interrupts; what are these? 

    While the clocks may be where they are at, the electrical timing may be off. With DP83867 RGMII, there is required setup/hold time. Our troubleshooting guide may be of help to you to further debug.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 30 points

    Hi Gerome,

    Sorry for being unclear. When we enabled MII loopback, we expected the packet sent by the EMAC driver would be routed back by the PHY, and the EMAC driver was supposed to get an interrupt if any data had arrived. But the EMAC driver didn't get anything.

    It looks the packets sent by the EMAC driver reaches our test PC, but the packets sent by the test PC fails to reach the EMAC driver. We will take a look at the troubleshooting guide.

    EMAC ------- coreRGMII -------- DP83867---------  test PC

    Thanks,

    Amy

  • 0 in reply to Amy Liu
    Prodigy 30 points

    Hi Gerome,

    The troubleshooting guide that we have (SNLA246B) doesn't cover 1000Mbps. Do you have those setup/hold time requirements for 1000Mbps?

    Thanks,

    Amy

  • 0 in reply to Amy Liu
    TI__Mastermind 34475 points

    Hi Amy,

    The same specs listed in guide applies for 1000Mbps even if no photos are given. It is even stricter as the frequency is a lot faster in 1000Mbps vs 10/100.

    It appears that from the block diagram provided that the RX pathway for the RGMII is having issues. I would suggest adjusting Reg 0x86 accordingly. In MII loopback, I would also ensure that 0x0 is forcing 1000Mbps via [6,13].

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 30 points

    Hi Gerome,

    Yes, we tried all the available RGMII_RX_DELAY_CTRL in 0x86, but no luck.

    And MII loopback doesn't seem working at 1000Mbps either. Here are the register settings to enable MII loopback.

    0x0000: Set bit 15 (RESET)

    0x0031: Clear bit 7 (INT_TST_MODE_1)

    0x0010: Clear bit 6 and 5 to disable auto-mdix

    0x0000: Set bit 12 and 9 to start auto-negotiation, bit 13 is 0, bit 6 is 1

    Once link is up:

    0x0000: Clear bit 12 to disable auto-negotiation

    0x0000: Set bit 14 to enable MII loopback

    0x00FE: Write 0xE720

    0x001F: Set bit 14 (SW_RESTART)

    Thanks,

    Amy

  • +1 in reply to Amy Liu
    TI__Mastermind 34475 points

    Hi Amy,

    I don't understand what setting Reg 0x0 for linkup is doing with regards to going for MII loopback. For loopback testing, you should be able to see packets so long as the layout is okay. I am also unsure of Could it be possible that the MAC timing is off? Perhaps measuring using a scope may be helpful to ensure setup and hold times are where they need to be. Can you also please provide the strapping registers 0x6E/F, as well as Reg 0x32?

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 30 points

    Hi Gerome,

    The Rx clock/data lines don't look good. We will investigate. I will close this issue for now.

    Thanks so much for your help!

    Amy